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IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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Journal of Electronic Testing: Theory and Applications - Special issue on On-line testing
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VTS '99 Proceedings of the 1999 17TH IEEE VLSI Test Symposium
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Proceedings of the 36th annual IEEE/ACM International Symposium on Microarchitecture
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VTS '07 Proceedings of the 25th IEEE VLSI Test Symmposium
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Proceedings of the 13th international symposium on Low power electronics and design
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Proceedings of the 46th Annual Design Automation Conference
Masking timing errors on speed-paths in logic circuits
Proceedings of the Conference on Design, Automation and Test in Europe
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NOCS '11 Proceedings of the Fifth ACM/IEEE International Symposium on Networks-on-Chip
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Proceedings of the International Conference on Computer-Aided Design
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Proceedings of the International Conference on Computer-Aided Design
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Proceedings of the Conference on Design, Automation and Test in Europe
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Proceedings of the 50th Annual Design Automation Conference
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Journal of Electronic Testing: Theory and Applications
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Proceedings of the International Conference on Computer-Aided Design
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Increasing dynamic variability with technology scaling has made it essential to incorporate large design-time timing margins to ensure yield and reliable operation. Online techniques for timing error resilience help recover timing margins, improving performance and/or power consumption. This paper presents TIMBER, a technique for online timing error resilience that masks timing errors by borrowing time from successive pipeline stages. TIMBER-based error masking can recover timing margins without instruction replay or roll-back support. Two sequential circuit elements --- TIMBER flip-flop and TIMBER latch --- that implement error masking based on time-borrowing are described. Both circuit elements are validated using corner-case circuit simulations, and the overhead and trade-offs of TIMBER-based error masking are evaluated on an industrial processor.