Effective Timing Error Tolerance in Flip-Flop Based Core Designs

Authors:
Stefanos Valadimas;Yiorgos Tsiatouhas;Angela Arapoyanni;Petros Xarchakos
Affiliations:
Department of Informatics and Telecommunications, University of Athens, Athens, Greece;Department of Computer Science and Engineering, University of Ioannina, Ioannina, Greece;Department of Informatics and Telecommunications, University of Athens, Athens, Greece;Department of Informatics and Telecommunications, University of Athens, Athens, Greece
Venue:
Journal of Electronic Testing: Theory and Applications
Year:
2013

Citing 16
Cited 0

On-Line Testing for VLSI—A Compendium of Approaches

Journal of Electronic Testing: Theory and Applications - Special issue on On-line testing
Cost reduction and evaluation of temporary faults detecting technique

DATE '00 Proceedings of the conference on Design, automation and test in Europe
Time Redundancy Based Soft-Error Tolerance to Rescue Nanometer Technologies

VTS '99 Proceedings of the 1999 17TH IEEE VLSI Test Symposium
Razor: A Low-Power Pipeline Based on Circuit-Level Timing Speculation

Proceedings of the 36th annual IEEE/ACM International Symposium on Microarchitecture
Making Typical Silicon Matter with Razor

Computer
A Circuit for Concurrent Detection of Soft and Timing Errors in Digital CMOS ICs

Journal of Electronic Testing: Theory and Applications
Robust System Design with Built-In Soft-Error Resilience

Computer
Circuit Failure Prediction and Its Application to Transistor Aging

VTS '07 Proceedings of the 25th IEEE VLSI Test Symmposium
Elastic Timing Scheme for Energy-Efficient and Robust Performance

ISQED '08 Proceedings of the 9th international symposium on Quality Electronic Design
Reliability Implications of Bias-Temperature Instability in Digital ICs

IEEE Design & Test
On-chip variability sensor using phase-locked loop for detecting and correcting parametric timing failures

IEEE Transactions on Very Large Scale Integration (VLSI) Systems
TIMBER: time borrowing and error relaying for online timing error resilience

Proceedings of the Conference on Design, Automation and Test in Europe
Timing error tolerance in nanometer ICs

IOLTS '10 Proceedings of the 2010 IEEE 16th International On-Line Testing Symposium
Efficient Fault Detection Architecture Design of Latch-Based Low Power DSP/MCU Processor

ETS '11 Proceedings of the 2011 Sixteenth IEEE European Test Symposium
Soft error correction in embedded storage elements

IOLTS '11 Proceedings of the 2011 IEEE 17th International On-Line Testing Symposium
Low Cost NBTI Degradation Detection and Masking Approaches

IEEE Transactions on Computers

Quantified Score

Hi-index	0.00

Visualization

Abstract

Timing errors turn to be a great concern in nanometer technology integrated circuits. This work presents a low-cost and power efficient, multiple timing error detection and correction technique for flip-flop based core designs. Two new flip-flop designs are introduced, which exploit a transition detector for timing error detection along with asynchronous local error correction schemes to provide timing error tolerance. The proposed, the Razor and the Time Dilation techniques were applied separately in the design of three versions of a 32-bit MIPS microprocessor core and the pci_bridge32 IWLS05 core, using a 90聽nm CMOS technology. Comparisons based on simulation results validate the efficiency of the new design approach.