A note on strongly fault-secure sequential circuits
IEEE Transactions on Computers
Design of Fast Self-Testing Checkers for a Class of Berger Codes
IEEE Transactions on Computers
Strongly Code Disjoint Checkers
IEEE Transactions on Computers
Efficient Design of Totally Self-Checking Checkers for all Low-Cost Arithmetic Codes
IEEE Transactions on Computers
Microprocessors & Microsystems
Design of High-Speed and Cost-Effective Self-Testing Checkers for Low-Cost Arithmetic Codes
IEEE Transactions on Computers
IEEE Transactions on Computers
Proportional BIC sensor for current testing
Journal of Electronic Testing: Theory and Applications - Special issue on IDDQ testing of VLSI circuits
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
Self-checking combinational circuit design for single and unidirectional multibit error
Journal of Electronic Testing: Theory and Applications
Theory of Transparent BIST for RAMs
IEEE Transactions on Computers
CMOS sensors for on-line thermal monitoring of VLSI circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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IEEE Transactions on Computers
Efficient Totally Self-Checking Shifter Design
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Clocked dosimeter compatible with digital CMOS technology
On-line testing for VLSI
Error Coding for Arithmetic Processors
Error Coding for Arithmetic Processors
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IEEE Transactions on Computers
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EDTC '95 Proceedings of the 1995 European conference on Design and Test
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EDTC '95 Proceedings of the 1995 European conference on Design and Test
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VTS '96 Proceedings of the 14th IEEE VLSI Test Symposium
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VTS '97 Proceedings of the 15th IEEE VLSI Test Symposium
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VTS '95 Proceedings of the 13th IEEE VLSI Test Symposium
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Journal of Electronic Testing: Theory and Applications
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Proceedings of the conference on Design, automation and test in Europe - Volume 1
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Journal of Electronic Testing: Theory and Applications
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Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
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Journal of Electronic Testing: Theory and Applications
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System-on-Chip Test Architectures: Nanometer Design for Testability
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Journal of Electronic Testing: Theory and Applications
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IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Microprocessors & Microsystems
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Proceedings of the 23rd ACM international conference on Great lakes symposium on VLSI
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Journal of Electronic Testing: Theory and Applications
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This paper presents an overview of a comprehensive collection of on-line testing techniques for VLSI. Such techniques are for instance: self-checking design, allowing highquality concurrent checking by means of hardware cost drastically lower than duplication; signature monitoring, allowing low cost concurrent error detection for FSMs; on-line monitoring ofreliability relevant parameters such as current, temperature, abnormal delay, signal activity during steady state, radiation dose, clock waveforms, etc.; exploitation of standard BIST, orimplementation of BIST techniques specific to on-line testing (Transparent BIST, Built-In ConcurrentSelf-Test,...); exploitation of scan paths to transfer internal states for performing varioustasks for on-line testing or fault tolerance; fail-safe techniques for VLSI, avoiding complex fail-safe interfaces using discrete components; radiation hardened designs, avoiding expensivefabrication process such as SOI, etc.