Processor Control Flow Monitoring Using Signatured Instruction Streams
IEEE Transactions on Computers
Built-in test for VLSI: pseudorandom techniques
Built-in test for VLSI: pseudorandom techniques
Optimized Synthesis of Concurrently Checked Controllers
IEEE Transactions on Computers
Pattern generation for a deterministic BIST scheme
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
Fault-tolerant computer system design
Fault-tolerant computer system design
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
On-Line Testing for VLSI—A Compendium of Approaches
Journal of Electronic Testing: Theory and Applications - Special issue on On-line testing
Self-checking and fault-tolerant digital design
Self-checking and fault-tolerant digital design
Altering a Pseudo-Random Bit Sequence for Scan-Based BIST
Proceedings of the IEEE International Test Conference on Test and Design Validity
Proceedings of the IEEE International Test Conference on Discover the New World of Test and Design
R-CBIST: an effective RAM-based input vector monitoring concurrent BIST technique
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Special ATPG to Correlate Test Patterns for Low-Overhead Mixed-Mode BIST
ATS '98 Proceedings of the 7th Asian Test Symposium
On the Necessity of On-line-BIST in Safety-Critical Applications - A Case-Study
FTCS '99 Proceedings of the Twenty-Ninth Annual International Symposium on Fault-Tolerant Computing
SPaRe: Selective Partial Replication for Concurrent Fault Detection in FSMs
VLSID '03 Proceedings of the 16th International Conference on VLSI Design
WHICH CONCURRENT ERROR DETECTION SCHEME TO CHOOSE?
ITC '00 Proceedings of the 2000 IEEE International Test Conference
Concurrent Fault Detection in Random Combinational Logic
ISQED '03 Proceedings of the 4th International Symposium on Quality Electronic Design
An Efficient Test Relaxation Technique for Combinational & Full-Scan Sequential Circuits
VTS '02 Proceedings of the 20th IEEE VLSI Test Symposium
Using Roving STARs for On-Line Testing and Diagnosis of FPGAs in Fault-Tolerant Applications
ITC '99 Proceedings of the 1999 IEEE International Test Conference
Design and reliability challenges in nanometer technologies
Proceedings of the 41st annual Design Automation Conference
Soft Errors in Advanced Computer Systems
IEEE Design & Test
Fault-Tolerant Systems
Synthesis of irregular combinational functions with large don't care sets
Proceedings of the 17th ACM Great Lakes symposium on VLSI
An Input Vector Monitoring Concurrent BIST Architecture Based on a Precomputed Test Set
IEEE Transactions on Computers
Selective Hardening in Early Design Steps
ETS '08 Proceedings of the 2008 13th European Test Symposium
Generating Hardware Assertion Checkers: For Hardware Verification, Emulation, Post-Fabrication Debugging and On-Line Monitoring
Concurrent Self-Test with Partially Specified Patterns for Low Test Latency and Overhead
ETS '09 Proceedings of the 2009 European Test Symposium
Cost-effective generation of minimal test sets for stuck-at faults in combinational logic circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IGRAINE-an Implication GRaph-bAsed engINE for fast implication, justification, and propagation
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
SPIRIT: a highly robust combinational test generation algorithm
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
XID: Don't care identification of test patterns for combinational circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Input vector monitoring on line concurrent BIST based on multilevel decoding logic
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
Journal of Electronic Testing: Theory and Applications
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Structural on-line self-test may be performed to detect permanent faults and avoid their accumulation in the system. This paper improves existing techniques for concurrent BIST that are based on a deterministic test set. Here, the test patterns are specially generated with a small number of specified bits. This results in very low test length and fault detection latency, which allows to frequently test critical faults. As a consequence, the likelihood of fault accumulation is reduced. Experiments with benchmark circuits show that the hardware overhead is significantly lower than the overhead of the state of the art. Moreover, a case-study on a super-scalar RISC processor demonstrates the feasibility of the method.