Built-in test for VLSI: pseudorandom techniques
Built-in test for VLSI: pseudorandom techniques
Cost-effective generation of minimal test sets for stuck-at faults in combinational logic circuits
DAC '93 Proceedings of the 30th international Design Automation Conference
IEEE Transactions on Computers - Special issue on fault-tolerant computing
COMPACTEST: A Method to Generate Compact Test Sets for Combinatorial Circuits
Proceedings of the IEEE International Test Conference on Test: Faster, Better, Sooner
Minimal Test Sets for Combinatorial Circuits
Proceedings of the IEEE International Test Conference on Test: Faster, Better, Sooner
Proceedings of the IEEE International Test Conference on Discover the New World of Test and Design
Critical path tracing - an alternative to fault simulation
DAC '83 Proceedings of the 20th Design Automation Conference
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
Algorithms to compute bridging fault coverage of IDDQ test sets
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Scalable Test Generators for High-Speed Datapath Circuits
Journal of Electronic Testing: Theory and Applications - Special issue on On-line testing
Mixed-Mode BIST Using Embedded Processors
Journal of Electronic Testing: Theory and Applications - Special issue on On-line testing
Test Data Decompression for Multiple Scan Designs with Boundary Scan
IEEE Transactions on Computers
Deterministic BIST with Multiple Scan Chains
Journal of Electronic Testing: Theory and Applications - Special issue on the IEEE European Test Workshop
Deterministic BIST with Partial Scan
Journal of Electronic Testing: Theory and Applications - special issue on the European test workshop 1999
Circuit partitioning for efficient logic BIST synthesis
Proceedings of the conference on Design, automation and test in Europe
On applying the set covering model to reseeding
Proceedings of the conference on Design, automation and test in Europe
GLSVLSI '01 Proceedings of the 11th Great Lakes symposium on VLSI
An exact solution to the minimum size test pattern problem
ACM Transactions on Design Automation of Electronic Systems (TODAES)
A mixed-mode BIST scheme based on folding compression
Journal of Computer Science and Technology
A Mixed Mode BIST Scheme Based on Reseeding of Folding Counters
Journal of Electronic Testing: Theory and Applications
Application of Deterministic Logic BIST on Industrial Circuits
Journal of Electronic Testing: Theory and Applications
On Using Twisted-Ring Counters for Test Set Embedding in BIST
Journal of Electronic Testing: Theory and Applications
An Efficient Deterministic Test Pattern Generator for Scan-Based BIST Environment
Journal of Electronic Testing: Theory and Applications
Two-Dimensional Test Data Compression for Scan-Based Deterministic BIST
Journal of Electronic Testing: Theory and Applications
Behavioral test generation for the selection of BIST Logic
Journal of Systems Architecture: the EUROMICRO Journal - Defect and fault tolerance in VLSI Systems
Test Set Embedding Based on Phase Shifters
EDCC-4 Proceedings of the 4th European Dependable Computing Conference on Dependable Computing
Deterministic BIST with multiple scan chains
ITC '98 Proceedings of the 1998 IEEE International Test Conference
An algorithmic approach to optimizing fault coverage for BIST logic synthesis
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Test vector decompression via cyclical scan chains and its application to testing core-based designs
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Accumulator based deterministic BIST
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Interaction of Constraint Programming and Local Search for Optimisation Problems
CP '01 Proceedings of the 7th International Conference on Principles and Practice of Constraint Programming
A Ring Architecture Strategy for BIST Test Pattern Generation
Journal of Electronic Testing: Theory and Applications
Efficient compression and application of deterministic patterns in a logic BIST architecture
Proceedings of the 40th annual Design Automation Conference
Built-in Test Pattern Generation For High-Performance Cir cuits Using Twisted-Ring Counters
VTS '99 Proceedings of the 1999 17TH IEEE VLSI Test Symposium
Non-Intrusive BIST for Systems-on-a-Chip
ITC '00 Proceedings of the 2000 IEEE International Test Conference
A MIXED MODE BIST SCHEME BASED ON RESEEDING OF FOLDING COUNTERS
ITC '00 Proceedings of the 2000 IEEE International Test Conference
Application of Deterministic Logic BIST on Industrial Circuits
ITC '00 Proceedings of the 2000 IEEE International Test Conference
ITC '01 Proceedings of the 2001 IEEE International Test Conference
Tailoring ATPG for Embedded Testing
ITC '01 Proceedings of the 2001 IEEE International Test Conference
Test Vector Encodin Usin Partial LFSR Reseedin
ITC '01 Proceedings of the 2001 IEEE International Test Conference
Low Hardware Overhead Scan Based 3-Weight Weighted Random BIST
ITC '01 Proceedings of the 2001 IEEE International Test Conference
TWO-DIMENSIONAL TEST DATA COMPRESSION FOR SCAN-BASED DETERMINISTIC BIST
ITC '01 Proceedings of the 2001 IEEE International Test Conference
Using BIST Control for Pattern Generation
ITC '97 Proceedings of the 1997 IEEE International Test Conference
On Using Machine Learning for Logic BIST
ITC '97 Proceedings of the 1997 IEEE International Test Conference
On Using Deterministic Test Sets in BIST
IOLTW '00 Proceedings of the 6th IEEE International On-Line Testing Workshop (IOLTW)
Test-decompression mechanism using a variable-length multiple-polynomial LFSR
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Analysis of Test Application Time for Test Data Compression Methods Based on Compression Codes
Journal of Electronic Testing: Theory and Applications
3-Stage Variable Length Continuous-Flow Scan Vector Decompression Scheme
VTS '04 Proceedings of the 22nd IEEE VLSI Test Symposium
On High-Quality, Low Energy Built-In Self Test Preparation at RT-Level
Journal of Electronic Testing: Theory and Applications
Achieving high encoding efficiency with partial dynamic LFSR reseeding
ACM Transactions on Design Automation of Electronic Systems (TODAES)
ISQED '05 Proceedings of the 6th International Symposium on Quality of Electronic Design
System-on-Chip Test Architectures: Nanometer Design for Testability
System-on-Chip Test Architectures: Nanometer Design for Testability
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
BISD: scan-based built-in self-diagnosis
Proceedings of the Conference on Design, Automation and Test in Europe
Efficient Concurrent Self-Test with Partially Specified Patterns
Journal of Electronic Testing: Theory and Applications
Test Set Compression Through Alternation Between Deterministic and Pseudorandom Test Patterns
Journal of Electronic Testing: Theory and Applications
On-chip area-efficient binary sequence storage
Proceedings of the 23rd ACM international conference on Great lakes symposium on VLSI
LFSR seed computation and reduction using SMT-based fault-chaining
Proceedings of the Conference on Design, Automation and Test in Europe
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Recently a deterministic built-in self-test scheme has been presented based on reseeding of multiple-polynomial linear feedback shift registers. This scheme encodes deterministic test sets at distinctly lower costs than previously known approaches. In this paper it is shown how this scheme can be supported during test pattern generation. The presented ATPG algorithm generates test sets which can be encoded very efficiently. Experiments show that the area required for synthesizing a BIST scheme that encodes these patterns is significantly less than the area needed for storing a compact test set. Furthermore, it is demonstrated that the proposed approach of combining ATPG and BIST synthesis leads to a considerably reduced hardware overhead compared to encoding a conventionally generated test set.