IEEE Transactions on Computers - Special issue on fault-tolerant computing
Pattern generation for a deterministic BIST scheme
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
Integration, the VLSI Journal - Special issue on VLSI testing
Diagnosis of Scan Cells in BIST Environment
IEEE Transactions on Computers
Effective diagnostics through interval unloads in a BIST environment
Proceedings of the 39th annual Design Automation Conference
Failure Diagnosis of Structured VLSI
IEEE Design & Test
Altering a Pseudo-Random Bit Sequence for Scan-Based BIST
Proceedings of the IEEE International Test Conference on Test and Design Validity
Special ATPG to Correlate Test Patterns for Low-Overhead Mixed-Mode BIST
ATS '98 Proceedings of the 7th Asian Test Symposium
Fault diagnosis based on effect-cause analysis: An introduction
DAC '80 Proceedings of the 17th Design Automation Conference
A Rapid and Scalable Diagnosis Scheme for BIST Environments with a Large Number of Scan Chains
VTS '00 Proceedings of the 18th IEEE VLSI Test Symposium
Application of Saluja-Karpovsky Compactors to Test Responses with Many Unknowns
VTS '03 Proceedings of the 21st IEEE VLSI Test Symposium
Application of Deterministic Logic BIST on Industrial Circuits
ITC '00 Proceedings of the 2000 IEEE International Test Conference
An Interval-Based Diagnosis Scheme for Identifying Failing Vectors in a Scan-BIST Environment
Proceedings of the conference on Design, automation and test in Europe
Diagnosis of Scan-Chains by Use of a Configurable Signature Register and Error-Correcting Codes
Proceedings of the conference on Design, automation and test in Europe - Volume 2
Scalable selector architecture for x-tolerant deterministic BIST
Proceedings of the 41st annual Design Automation Conference
X-masking during logic BIST and its impact on defect coverage
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Adaptive Debug and Diagnosis without Fault Dictionaries
ETS '07 Proceedings of the 12th IEEE European Test Symposium
Diagnosing at-speed scan BIST circuits using a low speed and low memory tester
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Test Encoding for Extreme Response Compaction
ETS '09 Proceedings of the 2009 European Test Symposium
Restrict Encoding for Mixed-Mode BIST
VTS '09 Proceedings of the 2009 27th IEEE VLSI Test Symposium
A diagnosis algorithm for extreme space compaction
Proceedings of the Conference on Design, Automation and Test in Europe
Scan-based BIST fault diagnosis
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
XID: Don't care identification of test patterns for combinational circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
X-compact: an efficient response compaction technique
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Finite memory test response compactors for embedded test applications
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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Built-In Self-Test (BIST) is less often applied to random logic than to embedded memories due to the following reasons: Firstly, for a satisfiable fault coverage it may be necessary to apply additional deterministic patterns, which cause additional hardware costs. Secondly, the BIST-signature reveals only poor diagnostic information. Recently, the first issue has been addressed successfully. The paper at hand proposes a viable, effective and cost efficient solution for the second problem. The paper presents a new method for Built-In Self-Diagnosis (BISD). The core of the method is an extreme response compaction architecture, which for the first time enables an autonomous on-chip evaluation of test responses with negligible hardware overhead. The key advantage of this architecture is that all data, which is relevant for a subsequent diagnosis, is gathered during just one test session. The BISD method comprises a hardware scheme, a test pattern generation approach and a diagnosis algorithm. Experiments conducted with industrial designs substantiate that the additional hardware overhead introduced by the BISD method is on average about 15% of the BIST area, and the same diagnostic resolution can be obtained as for external testing.