Diagnosis of Scan Cells in BIST Environment
IEEE Transactions on Computers
Improved fault diagnosis in scan-based BIST via superposition
Proceedings of the 37th Annual Design Automation Conference
Deterministic Partitioning Techniques for Fault Diagnosis in Scan-Based BIST
ITC '00 Proceedings of the 2000 IEEE International Test Conference
Improving the efficiency of error identification via signature analysis
VTS '95 Proceedings of the 13th IEEE VLSI Test Symposium
Fault Diagnosis in Scan-Based BIST Using Both Time and Space Information
ITC '99 Proceedings of the 1999 IEEE International Test Conference
Scan-based BIST fault diagnosis
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Embedded fault diagnosis in digital systems with BIST
Microprocessors & Microsystems
BISD: scan-based built-in self-diagnosis
Proceedings of the Conference on Design, Automation and Test in Europe
Diagnosis of logic circuits using compressed deterministic data and on-chip response comparison
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
| Hi-index | 0.00 |
Identifying fault-embedding scan cells is a significant challenge for fault diagnosis in scan-based BIST. Deterministic partitioning techniques provide cost-effective solutions to this problem. Both mathematical solutions and simulations on hardware implementations demonstrate the effectiveness of these techniques.