Introduction to algorithms
Multiple error detection and identification via signature analysis
Journal of Electronic Testing: Theory and Applications
Design of Self-Diagnostic Boards by Multiple Signature Analysis
IEEE Transactions on Computers
BIST Fault Diagnosis in Scan-Based VLSI Environments
Proceedings of the IEEE International Test Conference on Test and Design Validity
Fault Diagnosis in Scan-Based BIST
Proceedings of the IEEE International Test Conference
Critical path tracing - an alternative to fault simulation
DAC '83 Proceedings of the 20th Design Automation Conference
Improving the efficiency of error identification via signature analysis
VTS '95 Proceedings of the 13th IEEE VLSI Test Symposium
Identification of failing tests with cycling registers
ITC'88 Proceedings of the 1988 international conference on Test: new frontiers in testing
Diagnosis for scan-based BIST: reaching deep into the signatures
Proceedings of the conference on Design, automation and test in Europe
Effective diagnostics through interval unloads in a BIST environment
Proceedings of the 39th annual Design Automation Conference
Combinatorial group testing methods for the BIST diagnosis problem
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Journal of Electronic Testing: Theory and Applications
Compaction of pass/fail-based diagnostic test vectors for combinational and sequential circuits
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
Column Parity Row Selection (CPRS) BIST Diagnosis Technique: Modeling and Analysis
IEEE Transactions on Computers
Diagnosing at-speed scan BIST circuits using a low speed and low memory tester
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Embedded fault diagnosis in digital systems with BIST
Microprocessors & Microsystems
A Method of Locating Open Faults on Incompletely Identified Pass/Fail Information
IEICE - Transactions on Information and Systems
Fault Diagnosis on Multiple Fault Models by Using Pass/Fail Information
IEICE - Transactions on Information and Systems
Post-BIST Fault Diagnosis for Multiple Faults
IEICE - Transactions on Information and Systems
Diagnosis of logic circuits using compressed deterministic data and on-chip response comparison
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Fault Diagnosis with Orthogonal Compactors in Scan-Based Designs
Journal of Electronic Testing: Theory and Applications
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A new technique for diagnosis in a scan-based BISTenvironment is presented. It allows non-adaptiveidentification of both the scan cells that capture errors(space information) as well as a subset of the failing testvectors (time information). Having both space and timeinformation allows a faster and more precise diagnosis.Previous techniques for identifying the failing test vectorsduring BIST have been limited in the multiplicity of errorsthat can be handled and/or require a very large hardwareoverhead. The proposed approach, however, uses onlytwo cycling registers at the output of the scan chain toaccurately identify a subset of the failing BIST testvectors. This is accomplished using some novel pruningtechniques that efficiently extract information from thesignatures of the cycling registers. While not all thefailing BIST test vectors can be identified, results indicatethat a significant number of them can be. This additionalinformation can save a lot of time in failure analysis.