Multiple error detection and identification via signature analysis

Salvaging Test Windows in BIST Diagnostics

IEEE Transactions on Computers

Diagnosis of Scan Cells in BIST Environment

IEEE Transactions on Computers

Obtaining High Fault Coverage with Circular BIST Via State Skipping

VTS '97 Proceedings of the 15th IEEE VLSI Test Symposium

A Parameterized VHDL Library for On-Line Testing

ITC '97 Proceedings of the 1997 IEEE International Test Conference

FAULT DIAGNOSIS IN-SCAN-BASED BIST

ITC '97 Proceedings of the 1997 IEEE International Test Conference

Fault Diagnosis in Scan-Based BIST Using Both Time and Space Information

ITC '99 Proceedings of the 1999 IEEE International Test Conference

Diagnosis of Scan-Chains by Use of a Configurable Signature Register and Error-Correcting Codes

Proceedings of the conference on Design, automation and test in Europe - Volume 2

A Partition-Based Approach for Identifying Failing Scan Cells in Scan-BIST with Applications to System-on-Chip Fault Diagnosis

DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1

A Signature Analysis Technique for the Identification of Failing Vectors with Application to Scan-BIST*

Journal of Electronic Testing: Theory and Applications

Column Parity Row Selection (CPRS) BIST Diagnosis Technique: Modeling and Analysis

IEEE Transactions on Computers

Diagnosing at-speed scan BIST circuits using a low speed and low memory tester

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Fault Diagnosis with Orthogonal Compactors in Scan-Based Designs

Journal of Electronic Testing: Theory and Applications