Built-in test for VLSI: pseudorandom techniques
Built-in test for VLSI: pseudorandom techniques
Multiple error detection and identification via signature analysis
Journal of Electronic Testing: Theory and Applications
Improved fault diagnosis in scan-based BIST via superposition
Proceedings of the 37th Annual Design Automation Conference
Effective diagnostics through interval unloads in a BIST environment
Proceedings of the 39th annual Design Automation Conference
Failure Diagnosis of Structured VLSI
IEEE Design & Test
BIST Fault Diagnosis in Scan-Based VLSI Environments
Proceedings of the IEEE International Test Conference on Test and Design Validity
Fault Diagnosis in Scan-Based BIST
Proceedings of the IEEE International Test Conference
Efficient Signature-Based Fault Diagnosis Using Variable Size Windows
VLSID '01 Proceedings of the The 14th International Conference on VLSI Design (VLSID '01)
Salvaging test windows in BIST diagnostics
VTS '97 Proceedings of the 15th IEEE VLSI Test Symposium
A Rapid and Scalable Diagnosis Scheme for BIST Environments with a Large Number of Scan Chains
VTS '00 Proceedings of the 18th IEEE VLSI Test Symposium
Deterministic Partitioning Techniques for Fault Diagnosis in Scan-Based BIST
ITC '00 Proceedings of the 2000 IEEE International Test Conference
An Improved Fault Diagnosis Algorithm Based on Path Tracing with Dynamic Circuit Extraction
ITC '00 Proceedings of the 2000 IEEE International Test Conference
Fault Diagnosis in Scan-Based BIST Using Both Time and Space Information
ITC '99 Proceedings of the 1999 IEEE International Test Conference
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
IEICE - Transactions on Information and Systems
Diagnosing At-Speed Scan BIST Circuits Using a Low Speed and Low Memory Tester
ATS '06 Proceedings of the 15th Asian Test Symposium
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
BISD: scan-based built-in self-diagnosis
Proceedings of the Conference on Design, Automation and Test in Europe
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Numerous solutions have been proposed to reduce test data volume and test application time during manufacturing testing of digital devices. However, time to market challenge also requires a very efficient debug phase. Error identification in the test responses can become impractically slow in the debug phase due to large debug data, slow tester speed, and limited memory of the tester. In this paper, we investigate the problems and solutions related to using a relatively slow and limited memory tester to observe the at-speed behavior of fast circuits. Our method can identify all errors in at-speed scan BIST environment without any aliasing and using only little extra overhead by way of a multiplexer and masking circuit for diagnosis. Our solution takes into account the relatively slower speed of the tester and the reload time of the expected data to the tester memory due to limited tester memory while reducing the test/debug cost. Experimental results show that the test application time by our method can be reduced by a factor of 10 with very little hardware overhead to achieve such advantage.