BIST Fault Diagnosis in Scan-Based VLSI Environments

Diagnosis of Scan Cells in BIST Environment

IEEE Transactions on Computers

Effective diagnostics through interval unloads in a BIST environment

Proceedings of the 39th annual Design Automation Conference

A SAT Solver Using Reconfigurable Hardware and Virtual Logic

Journal of Automated Reasoning

A Virtual Logic Algorithm for Solving Satisfiability Problems Using Reconfigurable Hardware

FCCM '99 Proceedings of the Seventh Annual IEEE Symposium on Field-Programmable Custom Computing Machines

FAULT DIAGNOSIS IN-SCAN-BASED BIST

ITC '97 Proceedings of the 1997 IEEE International Test Conference

Diagnostic Techniques for the IBM S/390 600 MHz G5 Microprocessor

ITC '99 Proceedings of the 1999 IEEE International Test Conference

Fault Diagnosis in Scan-Based BIST Using Both Time and Space Information

ITC '99 Proceedings of the 1999 IEEE International Test Conference

A Partition-Based Approach for Identifying Failing Scan Cells in Scan-BIST with Applications to System-on-Chip Fault Diagnosis

DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1

A Signature Analysis Technique for the Identification of Failing Vectors with Application to Scan-BIST*

Journal of Electronic Testing: Theory and Applications

Column Parity Row Selection (CPRS) BIST Diagnosis Technique: Modeling and Analysis

IEEE Transactions on Computers

Diagnosing at-speed scan BIST circuits using a low speed and low memory tester

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

A Method of Locating Open Faults on Incompletely Identified Pass/Fail Information

IEICE - Transactions on Information and Systems

S/390 G5 CMOS microprocessor diagnostics

IBM Journal of Research and Development