Multiple error detection and identification via signature analysis
Journal of Electronic Testing: Theory and Applications
Diagnosis of Scan Cells in BIST Environment
IEEE Transactions on Computers
Improved fault diagnosis in scan-based BIST via superposition
Proceedings of the 37th Annual Design Automation Conference
BIST Fault Diagnosis in Scan-Based VLSI Environments
Proceedings of the IEEE International Test Conference on Test and Design Validity
A structured and scalable mechanism for test access to embedded reusable cores
ITC '98 Proceedings of the 1998 IEEE International Test Conference
A Rapid and Scalable Diagnosis Scheme for BIST Environments with a Large Number of Scan Chains
VTS '00 Proceedings of the 18th IEEE VLSI Test Symposium
Deterministic Partitioning Techniques for Fault Diagnosis in Scan-Based BIST
ITC '00 Proceedings of the 2000 IEEE International Test Conference
A Set of Benchmarks fo Modular Testing of SOCs
ITC '02 Proceedings of the 2002 IEEE International Test Conference
An Interval-Based Diagnosis Scheme for Identifying Failing Vectors in a Scan-BIST Environment
Proceedings of the conference on Design, automation and test in Europe
Fault Diagnosis in Scan-Based BIST Using Both Time and Space Information
ITC '99 Proceedings of the 1999 IEEE International Test Conference
Diagnosing at-speed scan BIST circuits using a low speed and low memory tester
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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We present a new partition-based fault diagnosis technique for identifying failing scan cells in a scan-BIST environment. This approach relies on a two-step scan chain partitioning scheme. In the first step, an interval-based partitioning scheme is used to generate a small number of partitions, where each element of a partition consists of a set of scan cells. In the second step, additional partitions are created using an earlier-proposed random-selection partitioning method. Two-step partitioning leads to higher diagnostic resolution than a scheme that relies only on random-selection partitioning, with only a small amount of additional hardware. The proposed scheme is especially suitable for a system-on-chip (SOC) composed of multiple embedded cores, where test access is provided by means of a TestRail that is threaded through the internal scan chains of the embedded cores. We present experimental results for the six largest ISCAS-89 benchmark circuits and for two SOCs crafted from some of the ISCAS-89 circuits.