Built-in test for VLSI: pseudorandom techniques
Built-in test for VLSI: pseudorandom techniques
IEEE Standards Intepretations: IEEE Std 1076-1987, IEEE Standard VHDL Language Reference Manual
IEEE Standards Intepretations: IEEE Std 1076-1987, IEEE Standard VHDL Language Reference Manual
Structured Logic Testing
A Tutorial on Built-in Self-Test. I. Principles
IEEE Design & Test
A Tutorial on Built-In Self-Test, Part 2: Applications
IEEE Design & Test
Design of compactors for signature-analyzers in built-in self-test
Proceedings of the IEEE International Test Conference 2001
BIST Fault Diagnosis in Scan-Based VLSI Environments
Proceedings of the IEEE International Test Conference on Test and Design Validity
Fault Diagnosis in Scan-Based BIST
Proceedings of the IEEE International Test Conference
Automated synthesis of large phase shifters for built-in self-test
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Salvaging test windows in BIST diagnostics
VTS '97 Proceedings of the 15th IEEE VLSI Test Symposium
A Rapid and Scalable Diagnosis Scheme for BIST Environments with a Large Number of Scan Chains
VTS '00 Proceedings of the 18th IEEE VLSI Test Symposium
Deterministic Partitioning Techniques for Fault Diagnosis in Scan-Based BIST
ITC '00 Proceedings of the 2000 IEEE International Test Conference
Diagnostic Techniques for the IBM S/390 600 MHz G5 Microprocessor
ITC '99 Proceedings of the 1999 IEEE International Test Conference
Fault Diagnosis in Scan-Based BIST Using Both Time and Space Information
ITC '99 Proceedings of the 1999 IEEE International Test Conference
Automated synthesis of phase shifters for built-in self-test applications
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Scalable selector architecture for x-tolerant deterministic BIST
Proceedings of the 41st annual Design Automation Conference
Journal of Computer Science and Technology
Diagnosing at-speed scan BIST circuits using a low speed and low memory tester
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Embedded fault diagnosis in digital systems with BIST
Microprocessors & Microsystems
Experimental comparison of different diagnosis algorithms in the BIST environment
ASM '07 The 16th IASTED International Conference on Applied Simulation and Modelling
BISD: scan-based built-in self-diagnosis
Proceedings of the Conference on Design, Automation and Test in Europe
Design and analysis of compact dictionaries for diagnosis in scan-BIST
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Diagnosis of logic circuits using compressed deterministic data and on-chip response comparison
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Construction and Analysis of Augmented Time Compactors
Journal of Electronic Testing: Theory and Applications
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Logic built-in self test (BIST) is increasingly being adopted to improve test quality and reduce test costs for rapidly growing designs. Compared to deterministic automated test pattern gener驴ation (ATPG), BIST presents inherent fault diagnostic challenges. Previous diagnostic techniques have been limited in their diagnosis resolution and/or require significant hardware overhead. This paper proposes an interval-based scan-unload method that ensures diagnosis resolution down to gate-level faults with minimal hard驴ware overhead. Tester fail-data collection is based on a novel con驴struct incorporated into the design-extensions of the standard test-interface language (STIL). The implementation of the proposed method is presented and analyzed.