Modifications of Competitive Group Testing
SIAM Journal on Computing
A new competitive algorithm for group testing
Discrete Applied Mathematics
Fault dictionary compaction by output sequence removal
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
Diagnosis of Scan Cells in BIST Environment
IEEE Transactions on Computers
Effective diagnostics through interval unloads in a BIST environment
Proceedings of the 39th annual Design Automation Conference
Efficient Signature-Based Fault Diagnosis Using Variable Size Windows
VLSID '01 Proceedings of the The 14th International Conference on VLSI Design (VLSID '01)
Dynamic diagnosis of sequential circuits based on stuck-at faults
VTS '96 Proceedings of the 14th IEEE VLSI Test Symposium
A Rapid and Scalable Diagnosis Scheme for BIST Environments with a Large Number of Scan Chains
VTS '00 Proceedings of the 18th IEEE VLSI Test Symposium
An Interval-Based Diagnosis Scheme for Identifying Failing Vectors in a Scan-BIST Environment
Proceedings of the conference on Design, automation and test in Europe
Gate Level Fault Diagnosis in Scan-Based BIST
Proceedings of the conference on Design, automation and test in Europe
Proceedings of the conference on Design, automation and test in Europe
Improving the efficiency of error identification via signature analysis
VTS '95 Proceedings of the 13th IEEE VLSI Test Symposium
Fault Diagnosis in Scan-Based BIST Using Both Time and Space Information
ITC '99 Proceedings of the 1999 IEEE International Test Conference
Combinatorial group testing methods for the BIST diagnosis problem
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
From Embedded Test to Embedded Diagnosis
ETS '05 Proceedings of the 10th IEEE European Symposium on Test
Fault Diagnosis in Integrated Circuits with BIST
DSD '07 Proceedings of the 10th Euromicro Conference on Digital System Design Architectures, Methods and Tools
Fault Diagnosis in Synchronous Sequential Circuits Based on an Effect-Cause Analysis
IEEE Transactions on Computers
Scan-based BIST fault diagnosis
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Creating small fault dictionaries [logic circuit fault diagnosis]
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A method of fault analysis for test generation and fault diagnosis
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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This paper presents an optimized fault diagnosing procedure applicable in Built-in Self-Test environments. Instead of the known approach based on a simple bisection of patterns in pseudorandom test sequences, we propose a novel bisection procedure where the diagnostic weight of test patterns is taken into account. Another novelty is the sequential nature of the procedure which allows pruning the search space. Opposite to the classical approach which targets all failing patterns, in the proposed method not all of such patterns are needed to be used for diagnosis. This allows to trade-off the speed of diagnosis with diagnostic resolution. To improve the diagnostic resolution multiple signature analyzers are used. A method is proposed to partition a single signature analyzer into a set of multiple independent analyzers, and the algorithms are given to synthesize an optimal interface between the outputs of the circuit under test and the analyzers. The proposed method is compared with three known fault diagnosis methods: classical Binary Search based on patterns bisection, Doubling and Jumping. Experimental results demonstrate the advantages of the proposed method compared to the previous ones.