Salvaging Test Windows in BIST Diagnostics
IEEE Transactions on Computers
Diagnosis of Scan Cells in BIST Environment
IEEE Transactions on Computers
Improved fault diagnosis in scan-based BIST via superposition
Proceedings of the 37th Annual Design Automation Conference
Diagnosis for scan-based BIST: reaching deep into the signatures
Proceedings of the conference on Design, automation and test in Europe
Obtaining High Fault Coverage with Circular BIST Via State Skipping
VTS '97 Proceedings of the 15th IEEE VLSI Test Symposium
Deterministic Partitioning Techniques for Fault Diagnosis in Scan-Based BIST
ITC '00 Proceedings of the 2000 IEEE International Test Conference
FAULT DIAGNOSIS IN-SCAN-BASED BIST
ITC '97 Proceedings of the 1997 IEEE International Test Conference
Fault Diagnosis in Scan-Based BIST Using Both Time and Space Information
ITC '99 Proceedings of the 1999 IEEE International Test Conference
Isolation of Failing Scan Cells through Convolutional Test Response Compaction
Journal of Electronic Testing: Theory and Applications
Embedded fault diagnosis in digital systems with BIST
Microprocessors & Microsystems
Fault Diagnosis with Orthogonal Compactors in Scan-Based Designs
Journal of Electronic Testing: Theory and Applications
| Hi-index | 0.01 |
Abstract: Efficient identification of all single bit errors in the input polynomial to signature analysis registers is achieved by using characteristic polynomial f(x)=f/sub a/(x)f/sub b/(x) where f/sub a/(x) and f/sub b/(x) have different degrees and are of the form f/sub n/(x)=x/sup n/+x/sup n-1/+1. The input polynomial must be of degree lcm(ord(f/sub a/(x)), ord(f/sub b/(x))), where lcm denotes the least common multiple. Diagnostic aliasing for multiple bit errors is reduced by using non-primitive polynomials for f/sub a/(x) and/or f/sub b/(x).