Diagnosis of Scan Cells in BIST Environment
IEEE Transactions on Computers
Discrete-event simulation
Failure Diagnosis of Structured VLSI
IEEE Design & Test
Design of Self-Diagnostic Boards by Multiple Signature Analysis
IEEE Transactions on Computers
An Efficient Scheme to Diagnose Scan Chains
Proceedings of the IEEE International Test Conference
A technique for fault diagnosis of defects in scan chains
Proceedings of the IEEE International Test Conference 2001
A Rapid and Scalable Diagnosis Scheme for BIST Environments with a Large Number of Scan Chains
VTS '00 Proceedings of the 18th IEEE VLSI Test Symposium
Deterministic Partitioning Techniques for Fault Diagnosis in Scan-Based BIST
ITC '00 Proceedings of the 2000 IEEE International Test Conference
Improving the efficiency of error identification via signature analysis
VTS '95 Proceedings of the 13th IEEE VLSI Test Symposium
Diagnosis of scan path failures
VTS '95 Proceedings of the 13th IEEE VLSI Test Symposium
Convolutional Compaction-Driven Diagnosis of Scan Failures
ETS '05 Proceedings of the 10th IEEE European Symposium on Test
FAULT DIAGNOSIS IN DESIGNSWITH CONVOLUTIONAL COMPACTORS
ITC '04 Proceedings of the International Test Conference on International Test Conference
Scan-based BIST fault diagnosis
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Identification of error-capturing scan cells in scan-BIST with applications to system-on-chip
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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This paper describes a non-recursive fault diagnosis technique for scan-based designs with convolutional test response compaction. The proposed approach allows a time-efficient and accurate identification of failing scan cells using Gauss---Jordan elimination method.