Evolutionary Optimization in Code-Based Test Compression
Proceedings of the conference on Design, Automation and Test in Europe - Volume 2
Using MUXs Network to Hide Bunches of Scan Chains
ISQED '05 Proceedings of the 6th International Symposium on Quality of Electronic Design
FCSCAN: an efficient multiscan-based test compression technique for test cost reduction
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
Constraint extraction for pseudo-functional scan-based delay testing
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Functional constraints vs. test compression in scan-based delay testing
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Survey of Test Vector Compression Techniques
IEEE Design & Test
Isolation of Failing Scan Cells through Convolutional Test Response Compaction
Journal of Electronic Testing: Theory and Applications
Test cost reduction for SoC using a combined approach to test data compression and test scheduling
Proceedings of the conference on Design, automation and test in Europe
SoC testing using LFSR reseeding, and scan-slice-based TAM optimization and test scheduling
Proceedings of the conference on Design, automation and test in Europe
Optimal Selective Huffman Coding for Test-Data Compression
IEEE Transactions on Computers
New test data decompressor for low power applications
Proceedings of the 44th annual Design Automation Conference
Test data compression scheme based on variable-to-fixed-plus-variable-length coding
Journal of Systems Architecture: the EUROMICRO Journal
X-Tolerant Compactor with On-Chip Registration and Signature-Based Diagnosis
IEEE Design & Test
Functional Constraints vs. Test Compression in Scan-Based Delay Testing
Journal of Electronic Testing: Theory and Applications
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
CacheCompress: a novel approach for test data compression with cache for IP embedded cores
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
GECOM: test data compression combined with all unknown response masking
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
A Selective Scan Slice Encoding Technique for Test Data Volume and Test Power Reduction
Journal of Electronic Testing: Theory and Applications
Proceedings of the conference on Design, automation and test in Europe
Scan chain organization for embedded diagnosis
Proceedings of the conference on Design, automation and test in Europe
State skip LFSRs: bridging the gap between test data compression and test set embedding for IP cores
Proceedings of the conference on Design, automation and test in Europe
A Test Data Compression Scheme for Reducing Power Based on OLELC and NBET
ICIC '08 Proceedings of the 4th international conference on Intelligent Computing: Advanced Intelligent Computing Theories and Applications - with Aspects of Theoretical and Methodological Issues
On capture power-aware test data compression for scan-based testing
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
Test Compression for IP Core Testing with Reconfigurable Network and Fixing-Flipping Coding
Journal of Electronic Testing: Theory and Applications
DX-compactor: distributed X-compaction for SoCs
Proceedings of the 19th ACM Great Lakes symposium on VLSI
Improving linear test data compression
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Deviation-based LFSR reseeding for test-data compression
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Scan-chain partition for high test-data compressibility and low shift power under routing constraint
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Scan power reduction in linear test data compression scheme
Proceedings of the 2009 International Conference on Computer-Aided Design
Low-power scan operation in test compression environment
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Power supply noise reduction for at-speed scan testing in linear-decompression environment
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Test Data Compression Using Multi-dimensional Pattern Run-length Codes
Journal of Electronic Testing: Theory and Applications
Improving compressed test pattern generation for multiple scan chain failure diagnosis
Proceedings of the Conference on Design, Automation and Test in Europe
A diagnosis algorithm for extreme space compaction
Proceedings of the Conference on Design, Automation and Test in Europe
LFSR-based test-data compression with self-stoppable seeds
Proceedings of the Conference on Design, Automation and Test in Europe
Seed selection in LFSR-reseeding-based test compression for the detection of small-delay defects
Proceedings of the Conference on Design, Automation and Test in Europe
Proceedings of the Conference on Design, Automation and Test in Europe
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems - Special section on the ACM IEEE international conference on formal methods and models for codesign (MEMOCODE) 2009
Test Set Compression Through Alternation Between Deterministic and Pseudorandom Test Patterns
Journal of Electronic Testing: Theory and Applications
Time-multiplexed compressed test of SOC designs
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Correlation-based rectangular encoding
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Nine-coded compression technique for testing embedded cores in socs
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Capture-power-aware test data compression using selective encoding
Integration, the VLSI Journal
Test data compression based on geometric shapes
Computers and Electrical Engineering
Test data compression using selective encoding of scan slices
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
SAT-based capture-power reduction for at-speed broadcast-scan-based test compression architectures
Proceedings of the 17th IEEE/ACM international symposium on Low-power electronics and design
Test Data Compression Using Selective Sparse Storage
Journal of Electronic Testing: Theory and Applications
Test data compression using interval broadcast scan for embedded cores
Microelectronics Journal
A new scheme of test data compression based on equal-run-length coding (ERLC)
Integration, the VLSI Journal
Achieving low capture and shift power in linear decompressor-based test compression environment
Microelectronics Journal
Test-data volume and scan-power reduction with low ATE interface for multi-core SoCs
Proceedings of the International Conference on Computer-Aided Design
Deterministic test vector compression / decompression using an embedded processor
EDCC'05 Proceedings of the 5th European conference on Dependable Computing
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Test data compression using four-coded and sparse storage for testing embedded core
ICA3PP'10 Proceedings of the 10th international conference on Algorithms and Architectures for Parallel Processing - Volume Part II
A new scan attack on RSA in presence of industrial countermeasures
COSADE'12 Proceedings of the Third international conference on Constructive Side-Channel Analysis and Secure Design
Techniques for SAT-based constrained test pattern generation
Microprocessors & Microsystems
Efficient SAT-based dynamic compaction and relaxation for longest sensitizable paths
Proceedings of the Conference on Design, Automation and Test in Europe
Scan power reduction for linear test compression schemes through seed selection
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Single cycle access structure for logic test
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Challenges and emerging solutions in testing TSV-based 2 1/2D- and 3D-stacked ICs
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
Efficient Test Compression Technique for SoC Based on Block Merging and Eight Coding
Journal of Electronic Testing: Theory and Applications
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This paper presents a novel test-data volume-compression methodology called the embedded deterministic test (EDT), which reduces manufacturing test cost by providing one to two orders of magnitude reduction in scan test data volume and scan test time. The presented scheme is widely applicable and easy to deploy because it is based on the standard scan/ATPG methodology and adopts a very simple flow. It is nonintrusive as it does not require any modifications to the core logic such as the insertion of test points or logic bounding unknown states. The EDT scheme consists of logic embedded on a chip and a new deterministic test-pattern generation technique. The main contributions of the paper are test-stimuli compression schemes that allow us to deliver test data to the on-chip continuous-flow decompressor. In particular, it can be done by repeating certain patterns at the rates, which are adjusted to the requirements of the test cubes. Experimental results show that for industrial circuits with test cubes with very low fill rates, ranging from 3% to 0.2%, these schemes result in compression ratios of 30 to 500 times. A comprehensive analysis of the encoding efficiency of the proposed compression schemes is also provided.