Enhanced reduced pin-count test for full-scan design
Proceedings of the IEEE International Test Conference 2001
Test Scheduling for Modular SOCs in an Abort-on-Fail Environment
ETS '05 Proceedings of the 10th IEEE European Symposium on Test
THE LEADING EDGE OF PRODUCTION WAFER PROBE TEST TECHNOLOGY
ITC '04 Proceedings of the International Test Conference on International Test Conference
Extending systems-on-chip to the third dimension: performance, cost and technological tradeoffs
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
3D Integration: Technology and Applications
3D Integration: Technology and Applications
IEEE Std 1500 Enables Modular SoC Testing
IEEE Design & Test
Test Data Volume Comparison: Monolithic vs. Modular SoC Testing
IEEE Design & Test
On-Chip TSV Testing for 3D IC before Bonding Using Sense Amplification
ATS '09 Proceedings of the 2009 Asian Test Symposium
Maximizing the functional yield of wafer-to-wafer 3-D integration
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Testing TSV-based three-dimensional stacked ICs
Proceedings of the Conference on Design, Automation and Test in Europe
Contactless testing: possibility or pipe-dream?
Proceedings of the Conference on Design, Automation and Test in Europe
Test Cost Analysis for 3D Die-to-Wafer Stacking
ATS '10 Proceedings of the 2010 19th IEEE Asian Test Symposium
DfT Architecture for 3D-SICs with Multiple Towers
ETS '11 Proceedings of the 2011 Sixteenth IEEE European Test Symposium
Input/Output Pad for Direct Contact and Contactless Testing
ETS '11 Proceedings of the 2011 Sixteenth IEEE European Test Symposium
Automation of 3D-DfT Insertion
ATS '11 Proceedings of the 2011 Asian Test Symposium
ATS '11 Proceedings of the 2011 Asian Test Symposium
A DfT Architecture for 3D-SICs Based on a Standardizable Die Wrapper
Journal of Electronic Testing: Theory and Applications
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Journal of Electronic Testing: Theory and Applications
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Through-Silicon Vias (TSVs) provide high-density, low-latency, and low-power vertical interconnects through a thinned-down wafer substrate, thereby enabling the creation of 2.5D- and 3D-Stacked ICs. In 2.5D-SICs, multiple dies are stacked side-by-side on top of a passive silicon interposer base containing TSVs. 3D-SICs are towers of vertically stacked active dies, in which the vertical inter-die interconnects contain TSVs. Both 2.5D- and 3D-SICs are fraught with test challenges, for which solutions are only emerging. In this paper, we classify the test challenges as (1) test flows, (2) test contents, and (3) test access.