Test-access mechanism optimization for core-based three-dimensional SOCs
Microelectronics Journal
Testing TSV-based three-dimensional stacked ICs
Proceedings of the Conference on Design, Automation and Test in Europe
Cost-effective integration of three-dimensional (3D) ICs emphasizing testing cost analysis
Proceedings of the International Conference on Computer-Aided Design
Test Impact on the Overall Die-to-Wafer 3D Stacked IC Cost
Journal of Electronic Testing: Theory and Applications
Fault Modeling and Multi-Tone Dither Scheme for Testing 3D TSV Defects
Journal of Electronic Testing: Theory and Applications
Comparing Through-Silicon-Via (TSV) Void/Pinhole Defect Self-Test Methods
Journal of Electronic Testing: Theory and Applications
Three-dimensional Integrated Circuits: Design, EDA, and Architecture
Foundations and Trends in Electronic Design Automation
TSV open defects in 3D integrated circuits: characterization, test, and optimal spare allocation
Proceedings of the 49th Annual Design Automation Conference
Small delay testing for TSVs in 3-D ICs
Proceedings of the 49th Annual Design Automation Conference
An enhanced double-TSV scheme for defect tolerance in 3D-IC
Proceedings of the Conference on Design, Automation and Test in Europe
In-situ method for TSV delay testing and characterization using input sensitivity analysis
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Challenges and emerging solutions in testing TSV-based 2 1/2D- and 3D-stacked ICs
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
ACM Journal on Emerging Technologies in Computing Systems (JETC)
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We present a novel testing scheme for TSVs in a 3D IC by performing on-chip TSV monitoring before bonding, using a sense amplification technique that is commonly seen on a DRAM. By virtue of the inherent capacitive characteristics, we can detect the faulty TSVs with little area overhead for the circuit under test.