Oscillation Ring Delay Test for High Performance Microprocessors
Journal of Electronic Testing: Theory and Applications - Special issue on microprocessor test and verification
All digital built-in delay and crosstalk measurement for on-chip buses
DATE '00 Proceedings of the conference on Design, automation and test in Europe
Oscillation ring based interconnect test scheme for SOC
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Journal of Electronic Testing: Theory and Applications
A low-overhead fault tolerance scheme for TSV-based 3D network on chip links
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
On-Chip TSV Testing for 3D IC before Bonding Using Sense Amplification
ATS '09 Proceedings of the 2009 Asian Test Symposium
Performance Characterization of TSV in 3D IC via Sensitivity Analysis
ATS '10 Proceedings of the 2010 19th IEEE Asian Test Symposium
Electrical Characterization for Intertier Connections and Timing Analysis for 3-D ICs
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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In this paper, we propose a method and the required architecture for characterizing the propagation delays of the through Silicon vias (TSVs) in a 3-D IC. First of all, every two TSVs are paired up to form an oscillation ring with some peripheral circuits. Their joint performance can thus be measured roughly by the oscillation period of the ring. Next, we utilize a technique called sensitivity analysis to further derive the propagation delay of each individual TSV participating in an oscillation ring--a distilling process. In this process, we perturb the strength of the two TSV drivers, and then measure their effects in terms of the change of the oscillation ring's period. By some following analysis, the propagation delay of each TSV can be revealed. On top of scheme, we also present an architecture that can activate the performance characterization process of each test unit--that consists of two TSVs--one at a time in a proper sequence. The area overhead is only 18.97 equivalent two-input NAND gate per TSV, by which one can gain the ability to profile the capacitances and the propagation delays of the TSVs on a 3-D IC.