Electrical Characterization for Intertier Connections and Timing Analysis for 3-D ICs

Authors:
Xiaoxia Wu;Wei Zhao;Mark Nakamoto;Chandra Nimmagadda;Durodami Lisk;Sam Gu;Riko Radojcic;Matt Nowak;Yuan Xie
Affiliations:
Qualcomm, San Diego,;Qualcomm, San Diego,;Qualcomm, San Diego,;Qualcomm, San Diego,;Qualcomm, San Diego,;Qualcomm, San Diego,;Qualcomm, San Diego,;Qualcomm, San Diego,;Department of Computer Science and Engineering, Penn State University, University Park,
Venue:
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Year:
2012

Citing 0
Cited 2

In-situ method for TSV delay testing and characterization using input sensitivity analysis

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Architecture and design of high-throughput, low-latency, and fault-tolerant routing algorithm for 3D-network-on-chip (3D-NoC)

The Journal of Supercomputing

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Abstract

Reducing interconnect delay and power consumption has become a major concern in deep submicron designs. 3-D technologies have been proposed as a promising solution to mitigate interconnect problems. This paper examines the electrical characterization of vertical intertier connections such as through silicon via (TSV) and microbumps considering process variations and studies their timing impact on the circuit level. We first provide parasitic RC characteristics of intertier connections including TSV and microbumps and examine their delay. Then circuit simulation is performed to evaluate the timing impact of intertier connections.