Planar-adaptive routing: low-cost adaptive networks for multiprocessors
ISCA '92 Proceedings of the 19th annual international symposium on Computer architecture
Planar-adaptive routing: low-cost adaptive networks for multiprocessors
Journal of the ACM (JACM)
ROMM routing on mesh and torus networks
Proceedings of the seventh annual ACM symposium on Parallel algorithms and architectures
IEEE Transactions on Parallel and Distributed Systems
Efficient exploration of the SoC communication architecture design space
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Universal schemes for parallel communication
STOC '81 Proceedings of the thirteenth annual ACM symposium on Theory of computing
A large scale, homogeneous, fully distributed parallel machine, I
ISCA '77 Proceedings of the 4th annual symposium on Computer architecture
A Fault-Tolerant Adaptive and Minimal Routing Approach in 3-D Meshes
ICPADS '00 Proceedings of the Seventh International Conference on Parallel and Distributed Systems
A simple fault-tolerant adaptive and minimal routing approach in 3-D meshes
Journal of Computer Science and Technology
Low-Latency Virtual-Channel Routers for On-Chip Networks
Proceedings of the 31st annual international symposium on Computer architecture
Near-Optimal Worst-Case Throughput Routing for Two-Dimensional Mesh Networks
Proceedings of the 32nd annual international symposium on Computer Architecture
Performance Evaluation and Design Trade-Offs for Network-on-Chip Interconnect Architectures
IEEE Transactions on Computers
A Gracefully Degrading and Energy-Efficient Modular Router Architecture for On-Chip Networks
Proceedings of the 33rd annual international symposium on Computer Architecture
Design space exploration for 3D architectures
ACM Journal on Emerging Technologies in Computing Systems (JETC)
Three-dimensional integrated circuits
IBM Journal of Research and Development - Advanced silicon technology
A novel dimensionally-decomposed router for on-chip communication in 3D architectures
Proceedings of the 34th annual international symposium on Computer architecture
Performance Evaluation for Three-Dimensional Networks-On-Chip
ISVLSI '07 Proceedings of the IEEE Computer Society Annual Symposium on VLSI
Tightly-Coupled Multi-Layer Topologies for 3-D NoCs
ICPP '07 Proceedings of the 2007 International Conference on Parallel Processing
MIRA: A Multi-layered On-Chip Interconnect Router Architecture
ISCA '08 Proceedings of the 35th Annual International Symposium on Computer Architecture
Proceedings of the 45th annual Design Automation Conference
Practical Deadlock-Free Fault-Tolerant Routing in Meshes Based on the Planar Network Fault Model
IEEE Transactions on Computers
Networks-on-chip in emerging interconnect paradigms: Advantages and challenges
NOCS '09 Proceedings of the 2009 3rd ACM/IEEE International Symposium on Networks-on-Chip
Design of NoC for SoC with Multiple Use Cases Requiring Guaranteed Performance
VLSID '10 Proceedings of the 2010 23rd International Conference on VLSI Design
Traffic- and Thermal-Aware Run-Time Thermal Management Scheme for 3D NoC Systems
NOCS '10 Proceedings of the 2010 Fourth ACM/IEEE International Symposium on Networks-on-Chip
The general matrix multiply-add operation on 2D torus
IPDPS'06 Proceedings of the 20th international conference on Parallel and distributed processing
Architecture and Design of Efficient 3D Network-on-Chip (3D NoC) for Custom Multicore SoC
BWCCA '10 Proceedings of the 2010 International Conference on Broadband, Wireless Computing, Communication and Applications
Advanced Design Issues for OASIS Network-on-Chip Architecture
BWCCA '10 Proceedings of the 2010 International Conference on Broadband, Wireless Computing, Communication and Applications
Proceedings of the Third International Workshop on Network on Chip Architectures
Comparative study of switching techniques for network-on-chip architecture
Proceedings of the 2011 International Conference on Communication, Computing & Security
A Low-Overhead Fault-Aware Deflection Routing Algorithm for 3D Network-on-Chip
ISVLSI '11 Proceedings of the 2011 IEEE Computer Society Annual Symposium on VLSI
A Two-Dimensional Low-Diameter Scalable On-Chip Network for Interconnecting Thousands of Cores
IEEE Transactions on Parallel and Distributed Systems
A Layer-Multiplexed 3D On-Chip Network Architecture
IEEE Embedded Systems Letters
Electrical Characterization for Intertier Connections and Timing Analysis for 3-D ICs
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
MCSOC '12 Proceedings of the 2012 IEEE 6th International Symposium on Embedded Multicore SoCs
Low-overhead Routing Algorithm for 3D Network-on-Chip
ICNC '12 Proceedings of the 2012 Third International Conference on Networking and Computing
AFRA: a low cost high performance reliable routing for 3D mesh NoCs
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
Graceful deadlock-free fault-tolerant routing algorithm for 3D Network-on-Chip architectures
Journal of Parallel and Distributed Computing
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Despite the higher scalability and parallelism integration offered by Network-on-Chip (NoC) over the traditional shared-bus based systems, it is still not an ideal solution for future large-scale Systems-on-Chip (SoCs), due to limitations such as high power consumption, high-cost communication, and low throughput. Recently, extending 2D-NoC to the third dimension (3D-NoC) has been proposed to deal with these problems; however, 3D-NoC systems are exposed to a variety of manufacturing and design factors making them vulnerable to different faults that cause corrupted message transfer or even catastrophic system failures. Therefore, a 3D-NoC system should be fault tolerant to transient malfunctions or permanent physical damages.In this paper, we propose a low-latency, high-throughput, and fault-tolerant routing algorithm named Look-Ahead-Fault-Tolerant (LAFT). LAFT reduces the communication latency and enhances the system performance while maintaining a reasonable hardware complexity and ensuring fault tolerance. We implemented the proposed algorithm on a real 3D-NoC architecture (3D-OASIS-NoC) and prototyped it on FPGA, then we evaluated its performance over various applications. Evaluation results show that the proposed algorithm efficiently reduces the communication latency that can reach an average of 38 % and 16 %, when compared to conventional XYZ and our early designed Look-Ahead-XYZ routing algorithms, respectively, and enhances the throughput with up to 46 % and 29 %.