Low-Latency Virtual-Channel Routers for On-Chip Networks

Authors:
Robert Mullins;Andrew West;Simon Moore
Affiliations:
University of Cambridge, UK;University of Cambridge, UK;University of Cambridge, UK
Venue:
Proceedings of the 31st annual international symposium on Computer architecture
Year:
2004

Citing 12
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Abstract

The on-chip communication requirements of manysystems are best served through the deployment of a regularchip-wide network. This paper presents the design of alow-latency on-chip network router for such applications.We remove control overheads (routing and arbitrationlogic) from the critical path in order to minimise cycle-timeand latency. Simulations illustrate that dramatic cycle timeimprovements are possible without compromising routerefficiency. Furthermore, these reductions permit flits to berouted in a single cycle, maximising the effectiveness of therouter's limited buffering resources.