Communications of the ACM
A generic architecture for on-chip packet-switched interconnections
DATE '00 Proceedings of the conference on Design, automation and test in Europe
Route packets, not wires: on-chip inteconnection networks
Proceedings of the 38th annual Design Automation Conference
A VLSI Architecture for Concurrent Data Structures
A VLSI Architecture for Concurrent Data Structures
IEEE Transactions on Parallel and Distributed Systems
Practical Design of Globally-Asynchronous Locally-Synchronous Systems
ASYNC '00 Proceedings of the 6th International Symposium on Advanced Research in Asynchronous Circuits and Systems
ASYNC '00 Proceedings of the 6th International Symposium on Advanced Research in Asynchronous Circuits and Systems
Clock Synchronization through Handshake Signalling
ASYNC '02 Proceedings of the 8th International Symposium on Asynchronus Circuits and Systems
Point to Point GALS Interconnect
ASYNC '02 Proceedings of the 8th International Symposium on Asynchronus Circuits and Systems
Self-Timed Ring for Globally-Asynchronous Locally-Synchronous Systems
ASYNC '03 Proceedings of the 9th International Symposium on Asynchronous Circuits and Systems
Self-Calibrating Clocks for Globally Asynchronous Locally Synchronous Systems
ICCD '00 Proceedings of the 2000 IEEE International Conference on Computer Design: VLSI in Computers & Processors
A Delay Model and Speculative Architecture for Pipelined Routers
HPCA '01 Proceedings of the 7th International Symposium on High-Performance Computer Architecture
Power-driven Design of Router Microarchitectures in On-chip Networks
Proceedings of the 36th annual IEEE/ACM International Symposium on Microarchitecture
Proceedings of the conference on Design, automation and test in Europe - Volume 2
A Power and Performance Model for Network-on-Chip Architectures
Proceedings of the conference on Design, automation and test in Europe - Volume 2
The Design and Test of a Smartcard Chip Using a CHAIN Self-Timed Network-on-Chip
Proceedings of the conference on Design, automation and test in Europe - Volume 3
QNoC: QoS architecture and design process for network on chip
Journal of Systems Architecture: the EUROMICRO Journal - Special issue: Networks on chip
Quality-of-service and error control techniques for network-on-chip architectures
Proceedings of the 14th ACM Great Lakes symposium on VLSI
Low-Latency Virtual-Channel Routers for On-Chip Networks
Proceedings of the 31st annual international symposium on Computer architecture
A Scheduling Discipline for Latency and Bandwidth Guarantees in Asynchronous Network-on-Chip
ASYNC '05 Proceedings of the 11th IEEE International Symposium on Asynchronous Circuits and Systems
An Asynchronous Router for Multiple Service Levels Networks on Chip
ASYNC '05 Proceedings of the 11th IEEE International Symposium on Asynchronous Circuits and Systems
An Asynchronous NOC Architecture Providing Low Latency Service and Its Multi-Level Design Framework
ASYNC '05 Proceedings of the 11th IEEE International Symposium on Asynchronous Circuits and Systems
Proceedings of the conference on Design, Automation and Test in Europe - Volume 2
Cost considerations in network on chip
Integration, the VLSI Journal - Special issue: Networks on chip and reconfigurable fabrics
Fast Asynchronous Shift Register for Bit-Serial Communication
ASYNC '06 Proceedings of the 12th IEEE International Symposium on Asynchronous Circuits and Systems
Design of On-chip and Off-chip Interfaces for a GALS NoC Architecture
ASYNC '06 Proceedings of the 12th IEEE International Symposium on Asynchronous Circuits and Systems
The design and implementation of a low-latency on-chip network
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
ViChaR: A Dynamic Virtual Channel Regulator for Network-on-Chip Routers
Proceedings of the 39th Annual IEEE/ACM International Symposium on Microarchitecture
High Rate Wave-pipelined Asynchronous On-chip Bit-serial Data Link
ASYNC '07 Proceedings of the 13th IEEE International Symposium on Asynchronous Circuits and Systems
A Power and Energy Exploration of Network-on-Chip Architectures
NOCS '07 Proceedings of the First International Symposium on Networks-on-Chip
High rate data synchronization in GALS socs
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Building asynchronous routers with independent sub-channels
SOC'09 Proceedings of the 11th international conference on System-on-chip
Statistical estimation and evaluation for communication mapping in Network-on-Chip
Integration, the VLSI Journal
Comparing Energy and Latency of Asynchronous and Synchronous NoCs for Embedded SoCs
NOCS '10 Proceedings of the 2010 Fourth ACM/IEEE International Symposium on Networks-on-Chip
Physical-Aware Link Allocation and Route Assignment for Chip Multiprocessing
NOCS '10 Proceedings of the 2010 Fourth ACM/IEEE International Symposium on Networks-on-Chip
A low latency wormhole router for asynchronous on-chip networks
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
Asynchronous spatial division multiplexing router
Microprocessors & Microsystems
Hermes-a - an asynchronous NoC router with distributed routing
PATMOS'10 Proceedings of the 20th international conference on Integrated circuit and system design: power and timing modeling, optimization and simulation
Link pipelining strategies for an application-specific asynchronous NoC
NOCS '11 Proceedings of the Fifth ACM/IEEE International Symposium on Networks-on-Chip
Asynchronous switching for low-power networks-on-chip
Microelectronics Journal
Proceedings of the Conference on Design, Automation and Test in Europe
Area efficient asynchronous SDM routers using 2-stage clos switches
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
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An asynchronous router for quality-of-service Networks on Chip (QNoC) is presented. It combines multiple service levels (SL) with multiple equal-priority virtual channels (VC) within each SL. VCs are assigned dynamically per packet in each router. The router employs fast arbitration schemes to minimize latency. Analytical expressions for a generic NoC router performance, area and power are derived, showing linear dependence on the number of buffers and flit width. The analytical results agree with QNoC router simulation results. The QNoC router architecture and specific asynchronous circuits are presented. When simulated on a 0.18@mm process, the router throughput ranges from 1.8 to 20Gbps for flits 8-128 bits wide.