Fault tolerance overhead in network-on-chip flow control schemes
SBCCI '05 Proceedings of the 18th annual symposium on Integrated circuits and system design
A survey of research and practices of Network-on-chip
ACM Computing Surveys (CSUR)
QNoC Asynchronous Router with Dynamic Virtual Channel Allocation
NOCS '07 Proceedings of the First International Symposium on Networks-on-Chip
A scalable, timing-safe, network-on-chip architecture with an integrated clock distribution method
Proceedings of the conference on Design, automation and test in Europe
Proceedings of the conference on Design, automation and test in Europe
Globally Asynchronous, Locally Synchronous Circuits: Overview and Outlook
IEEE Design & Test
Elastic Flow in an Application Specific Network-on-Chip
Electronic Notes in Theoretical Computer Science (ENTCS)
NOCS '08 Proceedings of the Second ACM/IEEE International Symposium on Networks-on-Chip
Developing mesochronous synchronizers to enable 3D NoCs
Proceedings of the conference on Design, automation and test in Europe
Integration, the VLSI Journal
Two-phase synchronization with sub-cycle latency
Integration, the VLSI Journal
Router designs for elastic buffer on-chip networks
Proceedings of the Conference on High Performance Computing Networking, Storage and Analysis
An asynchronous router with multicast support in NoC
CSS '07 Proceedings of the Fifth IASTED International Conference on Circuits, Signals and Systems
Asynchronous Bypass Channels: Improving Performance for Multi-synchronous NoCs
NOCS '10 Proceedings of the 2010 Fourth ACM/IEEE International Symposium on Networks-on-Chip
A fully-asynchronous low-power framework for GALS NoC integration
Proceedings of the Conference on Design, Automation and Test in Europe
aelite: a flit-synchronous network on chip with composable and predictable services
Proceedings of the Conference on Design, Automation and Test in Europe
An analytical model of broadcast in QoS-aware wormhole-routed NoCs
Journal of Systems and Software
Mesochronous NoC technology for power-efficient GALS MPSoCs
Proceedings of the Fifth International Workshop on Interconnection Network Architecture: On-Chip, Multi-Chip
Static timing analysis for modeling QoS in networks-on-chip
Journal of Parallel and Distributed Computing
Low-energy GALS NoC with FIFO-Monitoring dynamic voltage scaling
Microelectronics Journal
Proceedings of the Conference on Design, Automation and Test in Europe
Adaptive virtual channel partitioning for network-on-chip in heterogeneous architectures
ACM Transactions on Design Automation of Electronic Systems (TODAES) - Special Section on Networks on Chip: Architecture, Tools, and Methodologies
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Networks on Chip that can guarantee Quality of Service (QNoC) are based on special routers that can support multiple service levels. GALS SoCs call for asynchronous NoC implementations, to eliminate the need for synchronization when crossing clock domains. An asynchronous multi-service level QNoC router is investigated. It comprises multiple interconnected input and output ports, and arbitration mechanisms that resolve any output port and service level conflicts. Buffering and credit based transport are enabled, enhancing throughput. A synchronous and an asynchronous routers have been designed, and their performance is compared. The asynchronous router requires less area and enables a higher data rate.