Run-time voltage hopping for low-power real-time systems
Proceedings of the 37th Annual Design Automation Conference
A generic architecture for on-chip packet-switched interconnections
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Power Aware Design Methodologies
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Dynamic Voltage Scheduling for Real Time Asynchronous Systems
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Globally-asynchronous locally-synchronous systems (performance, reliability, digital)
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VSV: L2-Miss-Driven Variable Supply-Voltage Scaling for Low Power
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Independent front-end and back-end dynamic voltage scaling for a GALS microarchitecture
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Automatic phase detection for stochastic on-chip traffic generation
CODES+ISSS '06 Proceedings of the 4th international conference on Hardware/software codesign and system synthesis
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ACM Transactions on Architecture and Code Optimization (TACO)
Proceedings of the conference on Design, automation and test in Europe
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Variation-aware adaptive voltage scaling system
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
VLSID '08 Proceedings of the 21st International Conference on VLSI Design
Dynamic Voltage and Frequency Scaling Architecture for Units Integration within a GALS NoC
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Multisynchronous and Fully Asynchronous NoCs for GALS Architectures
IEEE Design & Test
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Integration, the VLSI Journal
Statistical physics approaches for network-on-chip traffic characterization
CODES+ISSS '09 Proceedings of the 7th IEEE/ACM international conference on Hardware/software codesign and system synthesis
Design and management of voltage-frequency island partitioned networks-on-chip
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
NOCS '10 Proceedings of the 2010 Fourth ACM/IEEE International Symposium on Networks-on-Chip
A High Throughput Low Power FIFO Used for GALS NoC Buffers
ISVLSI '10 Proceedings of the 2010 IEEE Annual Symposium on VLSI
PATMOS'06 Proceedings of the 16th international conference on Integrated Circuit and System Design: power and Timing Modeling, Optimization and Simulation
Dynamic Voltage Scaling for Multitasking Real-Time Systems With Uncertain Execution Time
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
An optimal energy and power model for dynamic voltage scaled multiprocessor systems
International Journal of Business Information Systems
Dynamic voltage and frequency scaling for shared resources in multicore processor designs
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In-network monitoring and control policy for DVFS of CMP networks-on-chip and last level caches
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International Journal of Business Information Systems
Proceedings of the Ninth IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis
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In this paper we propose two dynamic voltage scaling (DVS) policies for a GALS NoC, which is designed based on fully asynchronous switch architectures. The first one is a history-based DVS policy, which exploits the link utilization and adjusts the voltages of different parts of the router among a few voltage levels. The second one is a FIFO-adaptive DVS, which uses two FIFO threshold levels for decision making. It judiciously adjusts supply voltage of each switch among only three voltage levels. The introduced architecture is simulated in 90nm CMOS technology with accurate Spice simulations. Experimental results show that the FIFO-adaptive DVS not only lowers the implementation cost, but also in a 86% saturated network achieves 36% energy-delay product (ED) saving compared to the DVS policy based on link utilization.