Low-power operation using self-timed circuits and adaptive scaling of the supply voltage
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special issue on low-power design
Comparing algorithm for dynamic speed-setting of a low-power CPU
MobiCom '95 Proceedings of the 1st annual international conference on Mobile computing and networking
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Power considerations in the design of the Alpha 21264 microprocessor
DAC '98 Proceedings of the 35th annual Design Automation Conference
A survey of design techniques for system-level dynamic power management
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special section on low-power electronics and design
Operating-system directed power reduction
ISLPED '00 Proceedings of the 2000 international symposium on Low power electronics and design
Voltage scheduling in the IpARM microprocessor system
ISLPED '00 Proceedings of the 2000 international symposium on Low power electronics and design
Dynamic voltage scaling and power management for portable systems
Proceedings of the 38th annual Design Automation Conference
Comparing System-Level Power Management Policies
IEEE Design & Test
ASPRO-216: A Standard-Cell Q.D.I. 16-Bit RISC Asynchronous Microprocessor
ASYNC '98 Proceedings of the 4th International Symposium on Advanced Research in Asynchronous Circuits and Systems
Energy efficient CMOS microprocessor design
HICSS '95 Proceedings of the 28th Hawaii International Conference on System Sciences
Automatic monitoring for interactive performance and power reduction
Automatic monitoring for interactive performance and power reduction
Scheduling for reduced CPU energy
OSDI '94 Proceedings of the 1st USENIX conference on Operating Systems Design and Implementation
Dynamic Voltage and Frequency Scaling Architecture for Units Integration within a GALS NoC
NOCS '08 Proceedings of the Second ACM/IEEE International Symposium on Networks-on-Chip
Power reduction of asynchronous logic circuits using activity detection
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Low-energy GALS NoC with FIFO-Monitoring dynamic voltage scaling
Microelectronics Journal
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Power consumption is becoming a major issue for embedded systems design. High power consumption reduces battery life and affects system cost and performances. This paper introduces a new power reduction technique that combines an asynchronous processor and a low power operating system (OS). The asynchronous processor is ideal for embedded applications: it is low power and functional within a wide supply voltage range. According to the tasks requirements, the OS regulates the processor operating voltage and so the computational power at run-time. This ensures minimum energy consumption. Simulation results show that low power OS - asynchronous processor combination reduce drastically power consumption in a real-time embedded system.