Designing high performance CMOS microprocessors using full custom techniques
DAC '97 Proceedings of the 34th annual Design Automation Conference
Dynamic power management of electronic systems
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
ISPD '99 Proceedings of the 1999 international symposium on Physical design
System-level power optimization: techniques and tools
ISLPED '99 Proceedings of the 1999 international symposium on Low power electronics and design
System-level power optimization: techniques and tools
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Proceedings of the 37th Annual Design Automation Conference
Wattch: a framework for architectural-level power analysis and optimizations
Proceedings of the 27th annual international symposium on Computer architecture
ACM Transactions on Computer Systems (TOCS)
Modeling and forecasting of manufacturing variations (embedded tutorial)
Proceedings of the 2001 Asia and South Pacific Design Automation Conference
Reducing the complexity of the issue logic
ICS '01 Proceedings of the 15th international conference on Supercomputing
Future performance challenges in nanometer design
Proceedings of the 38th annual Design Automation Conference
Power and energy reduction via pipeline balancing
ISCA '01 Proceedings of the 28th annual international symposium on Computer architecture
Hardware and Software Techniques for Controlling DRAM Power Modes
IEEE Transactions on Computers
A scalable instruction queue design using dependence chains
ISCA '02 Proceedings of the 29th annual international symposium on Computer architecture
Reducing set-associative cache energy via way-prediction and selective direct-mapping
Proceedings of the 34th annual ACM/IEEE international symposium on Microarchitecture
Saving energy with just in time instruction delivery
Proceedings of the 2002 international symposium on Low power electronics and design
A microarchitectural-level step-power analysis tool
Proceedings of the 2002 international symposium on Low power electronics and design
A survey of design techniques for system-level dynamic power management
Readings in hardware/software co-design
On achieving balanced power consumption in software pipelined loops
CASES '02 Proceedings of the 2002 international conference on Compilers, architecture, and synthesis for embedded systems
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
IC power distribution challenges
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
Proceedings of the 10th international conference on Architectural support for programming languages and operating systems
Runtime Reconfiguration Techniques for Efficient General-Purpose Computation
IEEE Design & Test
HiPC '02 Proceedings of the 9th International Conference on High Performance Computing
HLSpower: Hybrid Statistical Modeling of the Superscalar Power-Performance Design Space
HiPC '02 Proceedings of the 9th International Conference on High Performance Computing
TEM2P2EST: A Thermal Enabled Multi-model Power/Performance ESTimator
PACS '00 Proceedings of the First International Workshop on Power-Aware Computer Systems-Revised Papers
Reordering Memory Bus Transactions for Reduced Power Consumption
LCTES '00 Proceedings of the ACM SIGPLAN Workshop on Languages, Compilers, and Tools for Embedded Systems
A Holistic Approach to System Level Energy Optimization
PATMOS '00 Proceedings of the 10th International Workshop on Integrated Circuit Design, Power and Timing Modeling, Optimization and Simulation
Dynamic Voltage Scheduling for Real Time Asynchronous Systems
PATMOS '02 Proceedings of the 12th International Workshop on Integrated Circuit Design. Power and Timing Modeling, Optimization and Simulation
Leakage power modeling and reduction with data retention
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Power-efficient issue queue design
Power aware computing
Control Techniques to Eliminate Voltage Emergencies in High Performance Processors
HPCA '03 Proceedings of the 9th International Symposium on High-Performance Computer Architecture
Deterministic Clock Gating for Microprocessor Power Reduction
HPCA '03 Proceedings of the 9th International Symposium on High-Performance Computer Architecture
A Power Perspective of Value Speculation for Superscalar Microprocessors
ICCD '00 Proceedings of the 2000 IEEE International Conference on Computer Design: VLSI in Computers & Processors
Elements of low power design for integrated systems
Proceedings of the 2003 international symposium on Low power electronics and design
Proceedings of the 2003 international symposium on Low power electronics and design
Microprocessor pipeline energy analysis
Proceedings of the 2003 international symposium on Low power electronics and design
Pipeline stage unification: a low-energy consumption technique for future mobile processors
Proceedings of the 2003 international symposium on Low power electronics and design
Exploiting compiler-generated schedules for energy savings in high-performance processors
Proceedings of the 2003 international symposium on Low power electronics and design
Current-mode signaling in deep submicrometer global interconnects
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special section on the 2001 international conference on computer design (ICCD)
Speculating to reduce unnecessary power consumption
ACM Transactions on Embedded Computing Systems (TECS)
VSV: L2-Miss-Driven Variable Supply-Voltage Scaling for Low Power
Proceedings of the 36th annual IEEE/ACM International Symposium on Microarchitecture
Access Pattern Restructuring for Memory Energy
IEEE Transactions on Parallel and Distributed Systems
Coupling compiler-enabled and conventional memory accessing for energy efficiency
ACM Transactions on Computer Systems (TOCS)
Exploiting Resonant Behavior to Reduce Inductive Noise
Proceedings of the 31st annual international symposium on Computer architecture
Power-aware compilation for register file energy reduction
International Journal of Parallel Programming - Special issue: Workshop on application specific processors (WASP)
Improved clock-gating through transparent pipelining
Proceedings of the 2004 international symposium on Low power electronics and design
Microarchitectural power modeling techniques for deep sub-micron microprocessors
Proceedings of the 2004 international symposium on Low power electronics and design
IBM Journal of Research and Development
The Power Grid Transient Simulation in Linear Time Based on 3D Alternating-Direction-Implicit Method
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
A low power architecture for embedded perception
Proceedings of the 2004 international conference on Compilers, architecture, and synthesis for embedded systems
Effective Adaptive Computing Environment Management via Dynamic Optimization
Proceedings of the international symposium on Code generation and optimization
Noise Aware Decoupling Capacitors for Multi-Voltage Power Distribution Systems
ISQED '05 Proceedings of the 6th International Symposium on Quality of Electronic Design
An efficient wakeup design for energy reduction in high-performance superscalar processors
Proceedings of the 2nd conference on Computing frontiers
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Instruction packing: reducing power and delay of the dynamic scheduling logic
ISLPED '05 Proceedings of the 2005 international symposium on Low power electronics and design
Power and thermal effects of SRAM vs. Latch-Mux design styles and clock gating choices
ISLPED '05 Proceedings of the 2005 international symposium on Low power electronics and design
Multi-story power delivery for supply noise reduction and low voltage operation
ISLPED '05 Proceedings of the 2005 international symposium on Low power electronics and design
Aggregating processor free time for energy reduction
CODES+ISSS '05 Proceedings of the 3rd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Combined circuit and architectural level variable supply-voltage scaling for low power
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Reducing latencies of pipelined cache accesses through set prediction
Proceedings of the 19th annual international conference on Supercomputing
Low-power, low-complexity instruction issue using compiler assistance
Proceedings of the 19th annual international conference on Supercomputing
Low-Power Design of 90-nm SuperH Processor Core
ICCD '05 Proceedings of the 2005 International Conference on Computer Design
Restrictive Compression Techniques to Increase Level 1 Cache Capacity
ICCD '05 Proceedings of the 2005 International Conference on Computer Design
Power-Efficient Wakeup Tag Broadcast
ICCD '05 Proceedings of the 2005 International Conference on Computer Design
Proceedings of the 38th annual IEEE/ACM International Symposium on Microarchitecture
"Flea-flicker" Multipass Pipelining: An Alternative to the High-Power Out-of-Order Offense
Proceedings of the 38th annual IEEE/ACM International Symposium on Microarchitecture
Control Speculation for Energy-Efficient Next-Generation Superscalar Processors
IEEE Transactions on Computers
Fast algorithms for IR drop analysis in large power grid
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
In-Line Interrupt Handling and Lock-Up Free Translation Lookaside Buffers (TLBs)
IEEE Transactions on Computers
Performance Models for Network Processor Design
IEEE Transactions on Parallel and Distributed Systems
Instruction packing: Toward fast and energy-efficient instruction scheduling
ACM Transactions on Architecture and Code Optimization (TACO)
A thermally-aware performance analysis of vertically integrated (3-D) processor-memory hierarchy
Proceedings of the 43rd annual Design Automation Conference
Decoupling capacitors for multi-voltage power distribution systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Self-checking instructions: reducing instruction redundancy for concurrent error detection
Proceedings of the 15th international conference on Parallel architectures and compilation techniques
SEED: scalable, efficient enforcement of dependences
Proceedings of the 15th international conference on Parallel architectures and compilation techniques
Throttling-Based Resource Management in High Performance Multithreaded Architectures
IEEE Transactions on Computers
A case for a complexity-effective, width-partitioned microarchitecture
ACM Transactions on Architecture and Code Optimization (TACO)
Modeling and analysis of leakage induced damping effect in low voltage LSIs
Proceedings of the 2006 international symposium on Low power electronics and design
IEEE Transactions on Computers
A Floorplan-Aware Dynamic Inductive Noise Controller for Reliable Processor Design
Proceedings of the 39th Annual IEEE/ACM International Symposium on Microarchitecture
Hybrid-scheduling for reduced energy consumption in high-performance processors
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
By-passing the out-of-order execution pipeline to increase energy-efficiency
Proceedings of the 4th international conference on Computing frontiers
Energy behavior of java applications from the memory perspective
JVM'01 Proceedings of the 2001 Symposium on JavaTM Virtual Machine Research and Technology Symposium - Volume 1
Reducing cache energy consumption by tag encoding in embedded processors
ISLPED '07 Proceedings of the 2007 international symposium on Low power electronics and design
The QC-2 parallel Queue processor architecture
Journal of Parallel and Distributed Computing
Dual-execution mode processor architecture
The Journal of Supercomputing
Dependability, power, and performance trade-off on a multicore processor
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
Low-power clock distribution in a multilayer core 3d microprocessor
Proceedings of the 18th ACM Great Lakes symposium on VLSI
Partial resolution for redundant operation table
Microprocessors & Microsystems
Journal of Systems Architecture: the EUROMICRO Journal
Improved Way Prediction Policy for Low-Energy Instruction Caches
ICESS '07 Proceedings of the 3rd international conference on Embedded Software and Systems
Static analysis of processor stall cycle aggregation
CODES+ISSS '08 Proceedings of the 6th IEEE/ACM/IFIP international conference on Hardware/Software codesign and system synthesis
Finding Stress Patterns in Microprocessor Workloads
HiPEAC '09 Proceedings of the 4th International Conference on High Performance Embedded Architectures and Compilers
HeDGE: Hybrid Dataflow Graph Execution in the Issue Logic
HiPEAC '09 Proceedings of the 4th International Conference on High Performance Embedded Architectures and Compilers
Context-sensitive static transistor-level IR analysis
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
Energy and performance evaluation of lossless file data compression on server systems
SYSTOR '09 Proceedings of SYSTOR 2009: The Israeli Experimental Systems Conference
Complexity Effective Bypass Networks
Transactions on High-Performance Embedded Architectures and Compilers II
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
An energy-efficient instruction scheduler design with two-level shelving and adaptive banking
Journal of Computer Science and Technology
A case for bufferless routing in on-chip networks
Proceedings of the 36th annual international symposium on Computer architecture
Proceedings of the 42nd Annual IEEE/ACM International Symposium on Microarchitecture
Early-stage definition of LPX: a low power issue-execute processor
PACS'02 Proceedings of the 2nd international conference on Power-aware computer systems
PACS'02 Proceedings of the 2nd international conference on Power-aware computer systems
Decoupled state-execute architecture
ISHPC'05/ALPS'06 Proceedings of the 6th international symposium on high-performance computing and 1st international conference on Advanced low power systems
Program phase detection based dynamic control mechanisms for pipeline stage unification adoption
ISHPC'05/ALPS'06 Proceedings of the 6th international symposium on high-performance computing and 1st international conference on Advanced low power systems
Reusing cached schedules in an out-of-order processor with in-order issue logic
ICCD'09 Proceedings of the 2009 IEEE international conference on Computer design
Proceedings of the 19th international conference on Parallel architectures and compilation techniques
An overview of achieving energy efficiency in on-chip networks
International Journal of Communication Networks and Distributed Systems
Reconfigurable ECO cells for timing closure and IR drop minimization
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Extraction error modeling and automated model debugging in high-performance custom designs
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
DCG: deterministic clock-gating for low-power microprocessor design
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special section on the 2002 international symposium on low-power electronics and design (ISLPED)
Energy-efficient hardware data prefetching
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Proceedings of 2011 International Conference for High Performance Computing, Networking, Storage and Analysis
PASCOM: power model for supercomputers
ARCS'06 Proceedings of the 19th international conference on Architecture of Computing Systems
Low power microprocessor design for embedded systems
ICCSA'06 Proceedings of the 2006 international conference on Computational Science and Its Applications - Volume Part IV
Instruction recirculation: eliminating counting logic in wakeup-free schedulers
Euro-Par'05 Proceedings of the 11th international Euro-Par conference on Parallel Processing
Single FU bypass networks for high clock rate superscalar processors
HiPC'04 Proceedings of the 11th international conference on High Performance Computing
Power reduction of superscalar processor functional units by resizing adder-width
PATMOS'05 Proceedings of the 15th international conference on Integrated Circuit and System Design: power and Timing Modeling, Optimization and Simulation
Power supply selective mapping for accurate timing analysis
PATMOS'05 Proceedings of the 15th international conference on Integrated Circuit and System Design: power and Timing Modeling, Optimization and Simulation
Runtime biased pointer reuse analysis and its application to energy efficiency
PACS'03 Proceedings of the Third international conference on Power - Aware Computer Systems
Hot-and-Cold: using criticality in the design of energy-efficient caches
PACS'03 Proceedings of the Third international conference on Power - Aware Computer Systems
Energy-Effective instruction fetch unit for wide issue processors
ACSAC'05 Proceedings of the 10th Asia-Pacific conference on Advances in Computer Systems Architecture
Bit-sliced datapath for energy-efficient high performance microprocessors
PACS'04 Proceedings of the 4th international conference on Power-Aware Computer Systems
Energy-aware data prefetching for general-purpose programs
PACS'04 Proceedings of the 4th international conference on Power-Aware Computer Systems
Finding extreme behaviors in microprocessor workloads
Transactions on High-Performance Embedded Architectures and Compilers IV
PICA: Processor Idle Cycle Aggregation for Energy-Efficient Embedded Systems
ACM Transactions on Embedded Computing Systems (TECS)
ACM Transactions on Architecture and Code Optimization (TACO)
Analysis and design of on-chip decoupling capacitors
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Low power wide gates for modern power efficient processors
Integration, the VLSI Journal
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Power dissipation is rapidly becoming a limiting factor in high performance microprocessor design due to ever increasing device counts and clock rates. The 21264 is a third generation Alpha microprocessor implementation, containing 15.2 million transistors and operating at 600 MHz. This paper describes some of the techniques the Alpha design team utilized to help manage power dissipation. In addition, the electrical design of the power, ground, and clock networks is presented.