Communications of the ACM
Simultaneous multithreading: maximizing on-chip parallelism
ISCA '95 Proceedings of the 22nd annual international symposium on Computer architecture
ISCA '95 Proceedings of the 22nd annual international symposium on Computer architecture
The filter cache: an energy efficient memory structure
MICRO 30 Proceedings of the 30th annual ACM/IEEE international symposium on Microarchitecture
The SimpleScalar tool set, version 2.0
ACM SIGARCH Computer Architecture News
Power considerations in the design of the Alpha 21264 microprocessor
DAC '98 Proceedings of the 35th annual Design Automation Conference
Reducing power in high-performance microprocessors
DAC '98 Proceedings of the 35th annual Design Automation Conference
Energy optimization of multilevel cache architectures for RISC and CISC processors
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Pipeline gating: speculation control for energy reduction
Proceedings of the 25th annual international symposium on Computer architecture
Content-addressable memory core cells: a survey
Integration, the VLSI Journal
An architectural solution for the inductive noise problem due to clock-gating
ISLPED '99 Proceedings of the 1999 international symposium on Low power electronics and design
Wattch: a framework for architectural-level power analysis and optimizations
Proceedings of the 27th annual international symposium on Computer architecture
Energy-driven integrated hardware-software optimizations using SimplePower
Proceedings of the 27th annual international symposium on Computer architecture
Optimization of high-performance superscalar architectures for energy efficiency
ISLPED '00 Proceedings of the 2000 international symposium on Low power electronics and design
Proceedings of the 33rd annual ACM/IEEE international symposium on Microarchitecture
Loop Transformations for Restructuring Compilers: The Foundations
Loop Transformations for Restructuring Compilers: The Foundations
Introduction to VLSI Systems
Deep-Submicron Microprocessor Design Issues
IEEE Micro
Design Challenges of Technology Scaling
IEEE Micro
Euro-Par '99 Proceedings of the 5th International Euro-Par Conference on Parallel Processing
Dynamic Thermal Management for High-Performance Microprocessors
HPCA '01 Proceedings of the 7th International Symposium on High-Performance Computer Architecture
Inherently lower-power high-performance superscalar architectures
Inherently lower-power high-performance superscalar architectures
Unified architecture level energy-efficiency metric
Proceedings of the 12th ACM Great Lakes symposium on VLSI
Low-complexity reorder buffer architecture
ICS '02 Proceedings of the 16th international conference on Supercomputing
A microarchitectural-level step-power analysis tool
Proceedings of the 2002 international symposium on Low power electronics and design
A survey of processors with explicit multithreading
ACM Computing Surveys (CSUR)
Optimizing pipelines for power and performance
Proceedings of the 35th annual ACM/IEEE international symposium on Microarchitecture
Power-Aware Control Speculation through Selective Throttling
HPCA '03 Proceedings of the 9th International Symposium on High-Performance Computer Architecture
Energy efficient co-adaptive instruction fetch and issue
Proceedings of the 30th annual international symposium on Computer architecture
Power efficient comparators for long arguments in superscalar processors
Proceedings of the 2003 international symposium on Low power electronics and design
Optimum Power/Performance Pipeline Depth
Proceedings of the 36th annual IEEE/ACM International Symposium on Microarchitecture
Energy-efficient issue queue design
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special section on low power
Fine-grained power management for multithreaded processor cores
Proceedings of the 2004 ACM symposium on Applied computing
Evaluation and choice of various branch predictors for low-power embedded processor
Journal of Computer Science and Technology
Software-Controlled Operand-Gating
Proceedings of the international symposium on Code generation and optimization: feedback-directed and runtime optimization
Specialized Dynamic Optimizations for High-Performance Energy-Efficient Microarchitecture
Proceedings of the international symposium on Code generation and optimization: feedback-directed and runtime optimization
Complexity-Effective Reorder Buffer Designs for Superscalar Processors
IEEE Transactions on Computers
Cycle-accurate power analysis for multiprocessor systems-on-a-chip
Proceedings of the 14th ACM Great Lakes symposium on VLSI
Energy Efficient Comparators for Superscalar Datapaths
IEEE Transactions on Computers
Power Awareness through Selective Dynamically Optimized Traces
Proceedings of the 31st annual international symposium on Computer architecture
Control Flow Modeling in Statistical Simulation for Accurate and Efficient Processor Design Studies
Proceedings of the 31st annual international symposium on Computer architecture
Improved clock-gating through transparent pipelining
Proceedings of the 2004 international symposium on Low power electronics and design
Understanding the energy efficiency of simultaneous multithreading
Proceedings of the 2004 international symposium on Low power electronics and design
An innovative low-power high-performance programmable signal processor for digital communications
IBM Journal of Research and Development
IBM Journal of Research and Development
Practical PACE for embedded systems
Proceedings of the 4th ACM international conference on Embedded software
Journal of Systems and Software - Special issue: Performance modeling and analysis of computer systems and networks
The optimum pipeline depth considering both power and performance
ACM Transactions on Architecture and Code Optimization (TACO)
Towards Efficient Supercomputing: A Quest for the Right Metric
IPDPS '05 Proceedings of the 19th IEEE International Parallel and Distributed Processing Symposium (IPDPS'05) - Workshop 11 - Volume 12
Improvement of Power-Performance Efficiency for High-End Computing
IPDPS '05 Proceedings of the 19th IEEE International Parallel and Distributed Processing Symposium (IPDPS'05) - Workshop 11 - Volume 12
IATAC: a smart predictor to turn-off L2 cache lines
ACM Transactions on Architecture and Code Optimization (TACO)
On the energy-efficiency of speculative hardware
Proceedings of the 2nd conference on Computing frontiers
Algorithmic problems in power management
ACM SIGACT News
Exploiting Structural Duplication for Lifetime Reliability Enhancement
Proceedings of the 32nd annual international symposium on Computer Architecture
Variable-Based Multi-module Data Caches for Clustered VLIW Processors
Proceedings of the 14th International Conference on Parallel Architectures and Compilation Techniques
Proceedings of the 14th International Conference on Parallel Architectures and Compilation Techniques
Dynamically configurable shared CMP helper engines for improved performance
ACM SIGARCH Computer Architecture News - Special issue: dasCMP'05
SC '05 Proceedings of the 2005 ACM/IEEE conference on Supercomputing
Cell Processor Low-Power Design Methodology
IEEE Micro
A cycle accurate power estimation tool
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
An integrated performance and power model for superscalar processor designs
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Thermal analysis of a 3D die-stacked high-performance microprocessor
GLSVLSI '06 Proceedings of the 16th ACM Great Lakes symposium on VLSI
Dynamic instruction schedulers in a 3-dimensional integration technology
GLSVLSI '06 Proceedings of the 16th ACM Great Lakes symposium on VLSI
Techniques for Multicore Thermal Management: Classification and New Exploration
Proceedings of the 33rd annual international symposium on Computer Architecture
LVS verification across multiple power domains for a quad-core microprocessor
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Power-aware scheduling for makespan and flow
Proceedings of the eighteenth annual ACM symposium on Parallelism in algorithms and architectures
Power-efficient instruction delivery through trace reuse
Proceedings of the 15th international conference on Parallel architectures and compilation techniques
Stall cycle redistribution in a transparent fetch pipeline
Proceedings of the 2006 international symposium on Low power electronics and design
Independent front-end and back-end dynamic voltage scaling for a GALS microarchitecture
Proceedings of the 2006 international symposium on Low power electronics and design
Proceedings of the 2006 international symposium on Low power electronics and design
Power efficiency for variation-tolerant multicore processors
Proceedings of the 2006 international symposium on Low power electronics and design
The exigency of benchmark and compiler drift: designing tomorrow's processors with yesterday's tools
Proceedings of the 20th annual international conference on Supercomputing
Accurate memory data flow modeling in statistical simulation
Proceedings of the 20th annual international conference on Supercomputing
ACM Transactions on Computer Systems (TOCS)
Speed scaling to manage energy and temperature
Journal of the ACM (JACM)
Lowering power in an experimental RISC processor
Microprocessors & Microsystems
Power macromodeling of MPSoC message passing primitives
ACM Transactions on Embedded Computing Systems (TECS) - Special Section LCTES'05
Energy efficient online deadline scheduling
SODA '07 Proceedings of the eighteenth annual ACM-SIAM symposium on Discrete algorithms
Speed scaling for weighted flow time
SODA '07 Proceedings of the eighteenth annual ACM-SIAM symposium on Discrete algorithms
Minimizing expected energy consumption in real-time systems through dynamic voltage scaling
ACM Transactions on Computer Systems (TOCS)
IEEE Transactions on Computers
Optimal Power/Performance Pipeline Depth for SMT in Scaled Technologies
IEEE Transactions on Computers
Efficiency trends and limits from comprehensive microarchitectural adaptivity
Proceedings of the 13th international conference on Architectural support for programming languages and operating systems
Communications of the ACM - Web science
Power management of variation aware chip multiprocessors
Proceedings of the 18th ACM Great Lakes symposium on VLSI
Getting the best response for your erg
ACM Transactions on Algorithms (TALG)
Stochastic DVS-based dynamic power management for soft real-time systems
Microprocessors & Microsystems
Competitive non-migratory scheduling for flow time and energy
Proceedings of the twentieth annual symposium on Parallelism in algorithms and architectures
ReVIVaL: A Variation-Tolerant Architecture Using Voltage Interpolation and Variable Latency
ISCA '08 Proceedings of the 35th Annual International Symposium on Computer Architecture
Instruction-driven clock scheduling with glitch mitigation
Proceedings of the 13th international symposium on Low power electronics and design
Speed Scaling with a Solar Cell
AAIM '08 Proceedings of the 4th international conference on Algorithmic Aspects in Information and Management
Speed Scaling Functions for Flow Time Scheduling Based on Active Job Count
ESA '08 Proceedings of the 16th annual European symposium on Algorithms
Speed scaling with an arbitrary power function
SODA '09 Proceedings of the twentieth Annual ACM-SIAM Symposium on Discrete Algorithms
ACM Transactions on Architecture and Code Optimization (TACO)
Efficient compilation for queue size constrained queue processors
Parallel Computing
Non-clairvoyant speed scaling for batched parallel jobs on multiprocessors
Proceedings of the 6th ACM conference on Computing frontiers
Improved Bounds for Speed Scaling in Devices Obeying the Cube-Root Rule
ICALP '09 Proceedings of the 36th International Colloquium on Automata, Languages and Programming: Part I
Sleep with Guilt and Work Faster to Minimize Flow Plus Energy
ICALP '09 Proceedings of the 36th International Colloquium on Automata, Languages and Programming: Part I
The bell is ringing in speed-scaled multiprocessor scheduling
Proceedings of the twenty-first annual symposium on Parallelism in algorithms and architectures
Dynamic thermal management using thin-film thermoelectric cooling
Proceedings of the 14th ACM/IEEE international symposium on Low power electronics and design
MicroFix: exploiting path-grained timing adaptability for improving power-performance efficiency
Proceedings of the 14th ACM/IEEE international symposium on Low power electronics and design
Energy-efficient register caching with compiler assistance
ACM Transactions on Architecture and Code Optimization (TACO)
Speed scaling with a solar cell
Theoretical Computer Science
Optimizing throughput and energy in online deadline scheduling
ACM Transactions on Algorithms (TALG)
Power-aware scheduling for makespan and flow
Journal of Scheduling
Parallel simulation of chip-multiprocessor by using multi-threading
AsiaMS '07 Proceedings of the IASTED Asian Conference on Modelling and Simulation
Selective replication: A lightweight technique for soft errors
ACM Transactions on Computer Systems (TOCS)
Tribeca: design for PVT variations with local recovery and fine-grained adaptation
Proceedings of the 42nd Annual IEEE/ACM International Symposium on Microarchitecture
Online deadline scheduling with bounded energy efficiency
TAMC'07 Proceedings of the 4th international conference on Theory and applications of models of computation
Energy efficient deadline scheduling in two processor systems
ISAAC'07 Proceedings of the 18th international conference on Algorithms and computation
On temperature-aware scheduling for single-processor systems
HiPC'07 Proceedings of the 14th international conference on High performance computing
Power-efficient, reliable microprocessor architectures: modeling and design methods
Proceedings of the 20th symposium on Great lakes symposium on VLSI
Interval-based models for run-time DVFS orchestration in superscalar processors
Proceedings of the 7th ACM international conference on Computing frontiers
Design and test strategies for microarchitectural post-fabrication tuning
ICCD'09 Proceedings of the 2009 IEEE international conference on Computer design
Implementation model for end hosts to achieve power-efficient data transmission
APCC'09 Proceedings of the 15th Asia-Pacific conference on Communications
Routing for energy minimization in the speed scaling model
INFOCOM'10 Proceedings of the 29th conference on Information communications
Applied inference: Case studies in microarchitectural design
ACM Transactions on Architecture and Code Optimization (TACO)
Runtime Energy Adaptation with Low-Impact Instrumented Code in a Power-Scalable Cluster System
CCGRID '10 Proceedings of the 2010 10th IEEE/ACM International Conference on Cluster, Cloud and Grid Computing
Deadline scheduling and power management for speed bounded processors
Theoretical Computer Science
Generating power-hungry test programs for power-aware validation of pipelined processors
SBCCI '10 Proceedings of the 23rd symposium on Integrated circuits and system design
Power and thermal characterization of POWER6 system
Proceedings of the 19th international conference on Parallel architectures and compilation techniques
Proceedings of the 19th international conference on Parallel architectures and compilation techniques
Non-clairvoyant scheduling for weighted flow time and energy on speed bounded processors
CATS '10 Proceedings of the Sixteenth Symposium on Computing: the Australasian Theory - Volume 109
An event-guided approach to reducing voltage noise in processors
Proceedings of the Conference on Design, Automation and Test in Europe
Distributed peak power management for many-core architectures
Proceedings of the Conference on Design, Automation and Test in Europe
Power and performance aware reconfigurable cache for CMPs
Proceedings of the Second International Forum on Next-Generation Multicore/Manycore Technologies
How to schedule when you have to buy your energy
APPROX/RANDOM'10 Proceedings of the 13th international conference on Approximation, and 14 the International conference on Randomization, and combinatorial optimization: algorithms and techniques
Power-efficient spilling techniques for chip multiprocessors
EuroPar'10 Proceedings of the 16th international Euro-Par conference on Parallel processing: Part I
Non-clairvoyant speed scaling for weighted flow time
ESA'10 Proceedings of the 18th annual European conference on Algorithms: Part I
Reducing the associativity and size of step caches in CRCW operation
IPDPS'06 Proceedings of the 20th international conference on Parallel and distributed processing
Profile-based optimization of power performance by using dynamic voltage scaling on a PC cluster
IPDPS'06 Proceedings of the 20th international conference on Parallel and distributed processing
Hardware-based power management for real-time applications
ISPDC'03 Proceedings of the Second international conference on Parallel and distributed computing
MicroFix: Using timing interpolation and delay sensors for power reduction
ACM Transactions on Design Automation of Electronic Systems (TODAES)
SWEEP: evaluating computer system energy efficiency using synthetic workloads
Proceedings of the 6th International Conference on High Performance and Embedded Architectures and Compilers
Speed Scaling for Weighted Flow Time
SIAM Journal on Computing
Speed scaling to manage temperature
TAPAS'11 Proceedings of the First international ICST conference on Theory and practice of algorithms in (computer) systems
Speed scaling for energy and performance with instantaneous parallelism
TAPAS'11 Proceedings of the First international ICST conference on Theory and practice of algorithms in (computer) systems
Predictive coordination of multiple on-chip resources for chip multiprocessors
Proceedings of the international conference on Supercomputing
Multiprocessor speed scaling for jobs with arbitrary sizes and deadlines
TAMC'11 Proceedings of the 8th annual conference on Theory and applications of models of computation
Evaluation of dynamic voltage and frequency scaling for stream programs
Proceedings of the 8th ACM International Conference on Computing Frontiers
CacheVisor: a toolset for visualizing shared caches in multicore and multithreaded processors
PaCT'11 Proceedings of the 11th international conference on Parallel computing technologies
Exploiting video stream similarity for energy-efficient decoding
MMM'07 Proceedings of the 13th International conference on Multimedia Modeling - Volume Part II
Speed scaling of tasks with precedence constraints
WAOA'05 Proceedings of the Third international conference on Approximation and Online Algorithms
Co-optimization of performance and power in a superscalar processor design
EUC'06 Proceedings of the 2006 international conference on Emerging Directions in Embedded and Ubiquitous Computing
Energy management for embedded multithreaded processors with integrated EDF scheduling
ARCS'05 Proceedings of the 18th international conference on Architecture of Computing Systems conference on Systems Aspects in Organic and Pervasive Computing
Design space navigation for neighboring power-performance efficient microprocessor configurations
ARCS'05 Proceedings of the 18th international conference on Architecture of Computing Systems conference on Systems Aspects in Organic and Pervasive Computing
Speed scaling to manage temperature
STACS'05 Proceedings of the 22nd annual conference on Theoretical Aspects of Computer Science
Exploiting media stream similarity for energy-efficient decoding and resource prediction
ACM Transactions on Embedded Computing Systems (TECS)
PARROT: power awareness through selective dynamically optimized traces
PACS'03 Proceedings of the Third international conference on Power - Aware Computer Systems
Improved multi-processor scheduling for flow time and energy
Journal of Scheduling
Routing for power minimization in the speed scaling model
IEEE/ACM Transactions on Networking (TON)
Towards efficient supercomputing: searching for the right efficiency metric
ICPE '12 Proceedings of the 3rd ACM/SPEC International Conference on Performance Engineering
Cost-effective power delivery to support per-core voltage domains for power-constrained processors
Proceedings of the 49th Annual Design Automation Conference
Auto-tuning for energy usage in scientific applications
Euro-Par'11 Proceedings of the 2011 international conference on Parallel Processing - Volume 2
A Multi-objective Approach for Workflow Scheduling in Heterogeneous Environments
CCGRID '12 Proceedings of the 2012 12th IEEE/ACM International Symposium on Cluster, Cloud and Grid Computing (ccgrid 2012)
Energy based performance tuning for large scale high performance computing systems
Proceedings of the 2012 Symposium on High Performance Computing
Energy-Efficient network routing with discrete cost functions
TAMC'12 Proceedings of the 9th Annual international conference on Theory and Applications of Models of Computation
Energy- and performance-aware scheduling of tasks on parallel and distributed systems
ACM Journal on Emerging Technologies in Computing Systems (JETC)
SWAT'12 Proceedings of the 13th Scandinavian conference on Algorithm Theory
Lucky scheduling for energy-efficient heterogeneous multi-core systems
HotPower'12 Proceedings of the 2012 USENIX conference on Power-Aware Computing and Systems
International Journal of Communication Networks and Distributed Systems
Scheduling for weighted flow time and energy with rejection penalty
Theoretical Computer Science
Using DVFS to optimize time warp simulations
Proceedings of the Winter Simulation Conference
Competitive online algorithms for multiple-machine power management and weighted flow time
CATS '13 Proceedings of the Nineteenth Computing: The Australasian Theory Symposium - Volume 141
IA^3 '13 Proceedings of the 3rd Workshop on Irregular Applications: Architectures and Algorithms
Improving the performance of actor model runtime environments on multicore and manycore platforms
Proceedings of the 2013 workshop on Programming based on actors, agents, and decentralized control
Multi-objective list scheduling of workflow applications in distributed computing infrastructures
Journal of Parallel and Distributed Computing
The Bell Is Ringing in Speed-Scaled Multiprocessor Scheduling
Theory of Computing Systems
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Power dissipation limits have emerged as a major constraint in the design of microprocessors. This is true not only at the low end, where cost and battery life are the primary drivers, but also now at the midrange and high-end system (server) level. Thus, the ability to estimate power consumption at the high level, during the early-stage definition and trade-off studies is a key new methodology enhancement sought by design and performance architects. We first review the fundamentals in terms of power estimation and power-performance trade-offs at the microarchitecture level. We then discuss the opportunities of saving power that can be exposed via microarchitecture-level modeling. In particular, the potential savings that can be effected through straightforward clock-gating techniques is cited as an example. We also describe some future ideas and trends in power-efficient processor design. Examples of how microarchitectural observations can be used toward power-saving circuit design optimizations are described. The design and modeling challenges are in the context of work in progress within IBM Research. This research is in support of future, high-end processor development within IBM.