Wattch: a framework for architectural-level power analysis and optimizations
Proceedings of the 27th annual international symposium on Computer architecture
System-level performance evaluation of three-dimensional integrated circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special issue on system-level interconnect prediction
Impact of three-dimensional architectures on interconnects in gigascale integration
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - System Level Design
Life is CMOS: why chase the life after?
Proceedings of the 39th annual Design Automation Conference
Design Challenges of Technology Scaling
IEEE Micro
Fabrication Technologies for Three-Dimensional Integrated Circuits
ISQED '02 Proceedings of the 3rd International Symposium on Quality Electronic Design
Temperature-aware microarchitecture
Proceedings of the 30th annual international symposium on Computer architecture
Temperature-aware microarchitecture: Modeling and implementation
ACM Transactions on Architecture and Code Optimization (TACO)
Technology, performance, and computer-aided design of three-dimensional integrated circuits
Proceedings of the 2004 international symposium on Physical design
Timing, energy, and thermal performance of three-dimensional integrated circuits
Proceedings of the 14th ACM Great Lakes symposium on VLSI
Efficient Thermal Placement of Standard Cells in 3D ICs using a Force Directed Approach
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
3D Processing Technology and Its Impact on iA32 Microprocessors
ICCD '04 Proceedings of the IEEE International Conference on Computer Design
Three-Dimensional Cache Design Exploration Using 3DCacti
ICCD '05 Proceedings of the 2005 International Conference on Computer Design
Implementing Caches in a 3D Technology for High Performance Processors
ICCD '05 Proceedings of the 2005 International Conference on Computer Design
Physical Design for 3D System on Package
IEEE Design & Test
Implementing Register Files for High-Performance Microprocessors in a Die-Stacked (3D) Technology
ISVLSI '06 Proceedings of the IEEE Computer Society Annual Symposium on Emerging VLSI Technologies and Architectures
Thermal-driven multilevel routing for 3-D ICs
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Floorplanning for 3-D VLSI design
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
A modular 3d processor for flexible product design and technology migration
Proceedings of the 5th conference on Computing frontiers
Investigating the effects of fine-grain three-dimensional integration on microarchitecture design
ACM Journal on Emerging Technologies in Computing Systems (JETC)
Trend and Challenge on System-on-a-Chip Designs
Journal of Signal Processing Systems
Three-dimensional Integrated Circuit Design
Three-dimensional Integrated Circuit Design
Design space exploration for 3-D cache
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Quantifying and coping with parametric variations in 3D-stacked microarchitectures
Proceedings of the 47th Design Automation Conference
Invited paper: Thermal modeling and analysis of 3D multi-processor chips
Integration, the VLSI Journal
Hardware trust implications of 3-D integration
WESS '10 Proceedings of the 5th Workshop on Embedded Systems Security
Thermal-aware memory mapping in 3D designs
Proceedings of the Conference on Design, Automation and Test in Europe
Emulation-based transient thermal modeling of 2D/3D systems-on-chip with active cooling
Microelectronics Journal
Thermal-aware floorplan schemes for reliable 3D multi-core processors
ICCSA'11 Proceedings of the 2011 international conference on Computational science and its applications - Volume Part II
3D NOC for many-core processors
Microelectronics Journal
Fuzzy control for enforcing energy efficiency in high-performance 3D systems
Proceedings of the International Conference on Computer-Aided Design
A qualitative security analysis of a new class of 3-d integrated crypto co-processors
Cryptography and Security
Design-time performance evaluation of thermal management policies for SRAM and RRAM based 3D MPSoCs
Proceedings of the great lakes symposium on VLSI
Thermal-aware real-time task scheduling for three-dimensional multicore chip
Proceedings of the 27th Annual ACM Symposium on Applied Computing
Spatial and temporal thermal characterization of stacked multicore architectures
ACM Journal on Emerging Technologies in Computing Systems (JETC)
Reducing memory reference energy with opportunistic virtual caching
Proceedings of the 39th Annual International Symposium on Computer Architecture
Adaptive dynamic frequency scaling for thermal-aware 3d multi-core processors
ICCSA'12 Proceedings of the 12th international conference on Computational Science and Its Applications - Volume Part IV
Thermomechanical stress-aware management for 3D IC designs
Proceedings of the Conference on Design, Automation and Test in Europe
Thermal-aware memory mapping in 3D designs
ACM Transactions on Embedded Computing Systems (TECS)
ACM Journal on Emerging Technologies in Computing Systems (JETC)
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3-dimensional integrated circuit (3D IC) technology places circuit blocks in the vertical dimension in addition to the conventional horizontal plane. Compared to conventional planar ICs, 3D ICs have shorter latencies as well as lower power consumption, due to shorter wires. The benefits of 3D ICs increase as we stack more die, due to successive reductions in wire lengths. However, as we stack more die, the power density increases due to increasing proximity of active (heat generating) devices, thus causing the temperatures to increase. Also, the topmost die on the 3D stack are located further from the heat sink and experience a longer heat dissipation path. Prior research has already identified thermal management as a critical issue in 3D technology. In this paper, we evaluate the thermal impact of building high-performance microprocessors in 3D. We estimate the temperatures of a planar IC based on the Alpha 21364 processor as well as 2-die and 4-die 3D implementations of the same. We show that, compared to the planar IC, the 2-die implementation and 4-die implementation increase the maximum temperature by 17 Kelvin and 33 Kelvin, respectively.