Three-Dimensional Cache Design Exploration Using 3DCacti
ICCD '05 Proceedings of the 2005 International Conference on Computer Design
Implementing Caches in a 3D Technology for High Performance Processors
ICCD '05 Proceedings of the 2005 International Conference on Computer Design
Demystifying 3D ICs: The Pros and Cons of Going Vertical
IEEE Design & Test
An automated design flow for 3D microarchitecture evaluation
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
Optimal topology exploration for application-specific 3D architectures
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
Thermal Trends in Emerging Technologies
ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
Thermal analysis of a 3D die-stacked high-performance microprocessor
GLSVLSI '06 Proceedings of the 16th ACM Great Lakes symposium on VLSI
Dynamic instruction schedulers in a 3-dimensional integration technology
GLSVLSI '06 Proceedings of the 16th ACM Great Lakes symposium on VLSI
Design and Management of 3D Chip Multiprocessors Using Network-in-Memory
Proceedings of the 33rd annual international symposium on Computer Architecture
Exploring compromises among timing, power and temperature in three-dimensional integrated circuits
Proceedings of the 43rd annual Design Automation Conference
PicoServer: using 3D stacking technology to enable a compact energy efficient chip multiprocessor
Proceedings of the 12th international conference on Architectural support for programming languages and operating systems
Die Stacking (3D) Microarchitecture
Proceedings of the 39th Annual IEEE/ACM International Symposium on Microarchitecture
Scalability of 3D-integrated arithmetic units in high-performance microprocessors
Proceedings of the 44th annual Design Automation Conference
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
A modular 3d processor for flexible product design and technology migration
Proceedings of the 5th conference on Computing frontiers
MIRA: A Multi-layered On-Chip Interconnect Router Architecture
ISCA '08 Proceedings of the 35th Annual International Symposium on Computer Architecture
An alternate design paradigm for low-power, low-cost, testable hybrid systems using scaled LTPS TFTs
ACM Journal on Emerging Technologies in Computing Systems (JETC)
PicoServer: Using 3D stacking technology to build energy efficient servers
ACM Journal on Emerging Technologies in Computing Systems (JETC)
Investigating the effects of fine-grain three-dimensional integration on microarchitecture design
ACM Journal on Emerging Technologies in Computing Systems (JETC)
Trend and Challenge on System-on-a-Chip Designs
Journal of Signal Processing Systems
Proceedings of the 2009 SPEC Benchmark Workshop on Computer Performance Evaluation and Benchmarking
Congestion-aware power grid optimization for 3D circuits using MIM and CMOS decoupling capacitors
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
Scan-chain design and optimization for three-dimensional integrated circuits
ACM Journal on Emerging Technologies in Computing Systems (JETC)
Design space exploration for 3-D cache
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
SSMCB: low-power variation-tolerant source-synchronous multicycle bus
IEEE Transactions on Circuits and Systems Part I: Regular Papers
Electrical modeling and characterization of through-silicon vias (TSVs) for 3-D integrated circuits
Microelectronics Journal
Interstratum connection design considerations for cost-effective 3-D system integration
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Invited paper: Thermal modeling and analysis of 3D multi-processor chips
Integration, the VLSI Journal
Test-access mechanism optimization for core-based three-dimensional SOCs
Microelectronics Journal
Rethinking thermal via planning with timing-power-temperature dependence for 3D ICs
Proceedings of the 16th Asia and South Pacific Design Automation Conference
Ultrasonic bonding for multi-chip packaging bonded with non-conductive film
Microelectronic Engineering
3D NOC for many-core processors
Microelectronics Journal
Proceedings of the ACM/SIGDA international symposium on Field Programmable Gate Arrays
Efficiently enabling conventional block sizes for very large die-stacked DRAM caches
Proceedings of the 44th Annual IEEE/ACM International Symposium on Microarchitecture
Optimization Methods for Post-Bond Testing of 3D Stacked ICs
Journal of Electronic Testing: Theory and Applications
Low-power gated bus synthesis for 3d ic via rectilinear shortest-path steiner graph
Proceedings of the 2012 ACM international symposium on International Symposium on Physical Design
Three-dimensional Integrated Circuits: Design, EDA, and Architecture
Foundations and Trends in Electronic Design Automation
Randomized partially-minimal routing: near-optimal oblivious routing for 3-D mesh networks
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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This short paper explores an implementation of a new technology called 3D die stacking and describes research activity at Intel.3D die stacking is the bonding of two die either face-to-face or face-to-back in order to construct the 3D structure.In this work a face-to-face bonding is utilized because it yields a higher density die-to-die inter-connect than is possible with face-to-back. With sufficiently dense die-to-die interconnect devices as complex as an iA32 microprocessor can be repartitioned or split between two die in order to simultaneously improve performance and power. The 3D structure of this emerging technology is examined and applied in this paper to a real x86 deeply pipelined high performance microprocessor.In this initial study, it is shown that a 3D implementation can potentially improve the performance by 15% while improving power by 15%.