Digital systems engineering
A bus delay reduction technique considering crosstalk
DATE '00 Proceedings of the conference on Design, automation and test in Europe
Interconnect tuning strategies for high-performance ICs
Proceedings of the conference on Design, automation and test in Europe
Concurrent flip-flop and repeater insertion for high performance integrated circuits
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Methodologies and Tools for Pipelined On-Chip Interconnect
ICCD '02 Proceedings of the 2002 IEEE International Conference on Computer Design: VLSI in Computers and Processors (ICCD'02)
Three-Dimensional Integrated Circuits: Performance, Design Methodology, and CAD Tools
ISVLSI '03 Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI'03)
Flip-Flop and Repeater Insertion for Early Interconnect Planning
Proceedings of the conference on Design, automation and test in Europe
Timing closure through a globally synchronous, timing partitioned design methodology
Proceedings of the 41st annual Design Automation Conference
A hybrid current/voltage mode on-chip signaling scheme with adaptive bandwidth capability
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
3D Processing Technology and Its Impact on iA32 Microprocessors
ICCD '04 Proceedings of the IEEE International Conference on Computer Design
A Skewed Repeater Bus Architecture for On-Chip Energy Reduction in Microprocessors
ICCD '05 Proceedings of the 2005 International Conference on Computer Design
Reducing the Data Switching Activity on Serial Link Buses
ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
Serial-link bus: a low-power on-chip bus architecture
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Interconnect opportunities for gigascale integration
IBM Journal of Research and Development
Theory of latency-insensitive design
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Optimum positioning of interleaved repeaters in bidirectional buses
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
On hamming product codes with type-II hybrid ARQ for on-chip interconnects
IEEE Transactions on Circuits and Systems Part I: Regular Papers
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In this paper, a variation-tolerant low-power source-synchronous multicycle bus (SSMCB) interconnect scheme is proposed. This scheme is scalable and suitable for transferring data across different clock domains such as those in "many-core" SoCs and in 3-D ICs. SSMCB replaces intermediate flip-flops by a source-synchronous synchronization scheme. Removing the intermediate flip-flops in the SSMCB scheme enables better averaging of delay variations across the whole interconnect, which reduces bit-rate degradation due to within-die process variations. Monte Carlo circuit simulations show that SSMCB eliminates 90% of the variation-induced performance degradation in a six-cycle 9-mm-long 16-bit conventional bus. The proposed multicycle bus scheme also leads to significant energy savings due to the elimination of power-hungry flip-flops and the efficient design of the source synchronization overhead. Moreover, eliminating the intermediate flip-flops avoids the timing overhead of the setup time, the flip-flop delay, and the single-cycle clock jitter. This delay slack can then be translated into further energy savings by downsizing the repeaters. The significant delay jitter due to capacitive coupling has been addressed, and solutions are put forward to alleviate it. Circuit simulations in a 65-nm process environment indicate that energy savings up to 20% are achievable for a six-cycle 9-mm-long 16-bit bus.