Flip-Flop and Repeater Insertion for Early Interconnect Planning

Authors:
R. Lu;G. Zhong;C. Koh;K. Chao
Affiliations:
ECE, Purdue University, West Lafayette, IN;ECE, Purdue University, West Lafayette, IN;ECE, Purdue University, West Lafayette, IN;Intel Corporation, Hillsboro, OR
Venue:
Proceedings of the conference on Design, automation and test in Europe
Year:
2002

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Abstract

We present a unified framework that considers flip-flopand repeater insertion and the placement of flip-flop/repeater blocks during RT or higher level design. Weintroduce the concept of independent feasible regions inwhich flip-flops and repeaters can be inserted in an inter-connectto satisfy both delay and cycle time constraints.Experimental results show that, with flip-flop insertion, wegreatly increase the ability of interconnects to meet timingconstraints. Our results also show that it is necessary toperform interconnect optimization at early design steps asthe optimization will have even greater impact on the chiplayout as feature size continually scales down.