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This paper proposes for latency insensitive systems a performanceoptimization technique called channel buffer queue sizing, whichis performed after relay station insertion in the physical designstage. It can be shown that proper queue sizing can reduce or evencompletely avoid the performance loss due to imbalanced relaystations insertion in reconvergent paths. Moreover, the problemof queue sizing and placement of the additional buffers for maximumperformance is formulated and studied to properly allocateavailable chip areas in the layout to communication channels. Analgorithm based on mixed integer linear programming is proposed.Experimental results show that queue sizing is effective in improvingthe performance of latency insensitive systems even under tightarea constraints. Moreover, the proposed algorithm is sufficientlyefficient in obtaining the optimal solution for systems of practicalsizes.