Graph-Based Algorithms for Boolean Function Manipulation
IEEE Transactions on Computers
On the models for asynchronous circuit behaviour with OR causality
Formal Methods in System Design
Reuse methodology manual: for system-on-a-chip designs
Reuse methodology manual: for system-on-a-chip designs
Surviving the SOC revolution: a guide to platform-based design
Surviving the SOC revolution: a guide to platform-based design
Performance analysis and optimization of latency insensitive systems
Proceedings of the 37th Annual Design Automation Conference
A methodology for correct-by-construction latency insensitive design
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
Synthesis and Optimization of Digital Circuits
Synthesis and Optimization of Digital Circuits
Unveiling the ISCAS-85 Benchmarks: A Case Study in Reverse Engineering
IEEE Design & Test
Coping with Latency in SOC Design
IEEE Micro
A Coarse-Grain Phased Logic CPU
ASYNC '03 Proceedings of the 9th International Symposium on Asynchronous Circuits and Systems
Low-Latency Contro Structures with Slack
ASYNC '03 Proceedings of the 9th International Symposium on Asynchronous Circuits and Systems
Methodologies and Tools for Pipelined On-Chip Interconnect
ICCD '02 Proceedings of the 2002 IEEE International Conference on Computer Design: VLSI in Computers and Processors (ICCD'02)
Generalized Latency-Insensitive Systems for Single-Clock and Multi-Clock Architectures
Proceedings of the conference on Design, automation and test in Europe - Volume 2
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
An architecture and a wrapper synthesis approach for multi-clock latency-insensitive systems
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Performance analysis of concurrent systems with early evaluation
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
Topology-based optimization of maximal sustainable throughput in a latency-insensitive system
Proceedings of the 44th annual Design Automation Conference
Synchronous elastic circuits with early evaluation and token counterflow
Proceedings of the 44th annual Design Automation Conference
Adaptive Latency-Insensitive Protocols
IEEE Design & Test
Performance Evaluation of Asynchronous Concurrent Systems Using Petri Nets
IEEE Transactions on Software Engineering
Using functional independence conditions to optimize the performance of latency-insensitive systems
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
MEMOCODE '07 Proceedings of the 5th IEEE/ACM International Conference on Formal Methods and Models for Codesign
System-level design: orthogonalization of concerns and platform-based design
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Theory of latency-insensitive design
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Early evaluation for performance enhancement in phased logic
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Performance analysis of latency-insensitive systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A formal framework for interfacing mixed-timing systems
Integration, the VLSI Journal
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Latency-insensitive design is a methodology for system-on-chip (SoC) design that simplifies the reuse of intellectual property cores and the implementation of the communication among them. This simplification is based on a system-level protocol that decouples the intracore logic design from the design of the intercore communication channels. Each core is encapsulated within a shell, a synthesized logic block that dynamically controls its operation to interface it with the rest of the SoC and absorb any latency variations on its I/O signals. In particular, a shell stalls a core whenever new valid data are not available on the input channels or a downlink core has requested a delay in the data production on the output channels. We study how knowledge about the internal logic structure of a core can be applied to the design of its shell to improve the overall system-level performance by avoiding unnecessary local stalling. We introduce the notion of functional independence condition (FIC) and present a novel circuit design of a generic shell template that can leverage FIC. We propose a procedure for the logic synthesis of a FIC-shell instance that is only based on the analysis of the intracore logic and does not require any input from the designers. Finally, we present a comprehensive experimental analysis that shows the performance benefits and limited design overhead of the proposed technique. This includes the semicustom design of an SoC, an ultrawideband baseband transmitter, using a 90-nm industrial standard cell library.