A unified signal transition graph model for asynchronous control circuit synthesis
ICCAD '92 1992 IEEE/ACM international conference proceedings on Computer-aided design
Concurrent hardware: the theory and practice of self-timed design
Concurrent hardware: the theory and practice of self-timed design
On the models for asynchronous circuit behaviour with OR causality
Formal Methods in System Design
Partial order verification with PEP
POMIV '96 Proceedings of the DIMACS workshop on Partial order methods in verification
Canonical Prefixes of Petri Net Unfoldings
CAV '02 Proceedings of the 14th International Conference on Computer Aided Verification
Two Alterative Definitions of Synchronic Distance
Selected Papers from the First and the Second European Workshop on Application and Theory of Petri Nets
A FIFO Ring Performance Experiment
ASYNC '97 Proceedings of the 3rd International Symposium on Advanced Research in Asynchronous Circuits and Systems
ASYNC '98 Proceedings of the 4th International Symposium on Advanced Research in Asynchronous Circuits and Systems
ASYNC '99 Proceedings of the 5th International Symposium on Advanced Research in Asynchronous Circuits and Systems
ASYNC '99 Proceedings of the 5th International Symposium on Advanced Research in Asynchronous Circuits and Systems
ASYNC '99 Proceedings of the 5th International Symposium on Advanced Research in Asynchronous Circuits and Systems
ASYNC '00 Proceedings of the 6th International Symposium on Advanced Research in Asynchronous Circuits and Systems
ASYNC '01 Proceedings of the 7th International Symposium on Asynchronous Circuits and Systems
Asynchronous Circuit Synthesis by Direct Mapping: Interfacing to Environment
ASYNC '02 Proceedings of the 8th International Symposium on Asynchronus Circuits and Systems
The Design of an Asynchronous MIPS R3000 Microprocessor
ARVLSI '97 Proceedings of the 17th Conference on Advanced Research in VLSI (ARVLSI '97)
Practical verification and synthesis of low latency asynchronous systems
Practical verification and synthesis of low latency asynchronous systems
The VLSI-programming language tangram and its translation into handshake circuits
EURO-DAC '91 Proceedings of the conference on European design automation
Direct Implementation of Asynchronous Control Units
IEEE Transactions on Computers
Principles of Asynchronous Circuit Design: A Systems Perspective
Principles of Asynchronous Circuit Design: A Systems Perspective
Analysis of Static Data Flow Structures
Fundamenta Informaticae - Application of Concurrency to System Design, the Sixth Special Issue
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Analysis of Static Data Flow Structures
Fundamenta Informaticae - Application of Concurrency to System Design, the Sixth Special Issue
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OR-causality , or weak precedence, is a way to increase performance of asynchronous circuit in on-chip interfacing, computation process control, early evaluation in data-flow structures, error-recovery etc. The difficulties in hazard-free implementation of OR-causality restricted itsuse to the simplest cases of merging. We advance this subject by introducing slack in the taxonomy of OR-causality, which allows latency reduction to be achieved in the context of highly pipelined operation. Petri net model and circuit structures are proposed for the bounded and "almost" unbounded merge cases. The specifics of data or control token stream merging are studied in a number of examples. Those show the applicability of the new merge constructs to a wide range of functional operators, including arithmetic, Boolean and threshold functions.