Direct synthesis of timed asynchronous circuits
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
Logic Synthesis and Verification
Automatic Abstraction for Verification of Timed Circuits and Systems
CAV '01 Proceedings of the 13th International Conference on Computer Aided Verification
ASYNC '99 Proceedings of the 5th International Symposium on Advanced Research in Asynchronous Circuits and Systems
A Counterflow Pipeline Experiment
ASYNC '99 Proceedings of the 5th International Symposium on Advanced Research in Asynchronous Circuits and Systems
Congestion and Starvation Detection in Ripple FIFOs
ASYNC '03 Proceedings of the 9th International Symposium on Asynchronous Circuits and Systems
Low-Latency Contro Structures with Slack
ASYNC '03 Proceedings of the 9th International Symposium on Asynchronous Circuits and Systems
Design automation of real-life asynchronous devices and systems
Foundations and Trends in Electronic Design Automation
A scalable dual-clock FIFO for data transfers between arbitrary and haltable clock domains
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A modular synchronizing FIFO for NoCs
NOCS '09 Proceedings of the 2009 3rd ACM/IEEE International Symposium on Networks-on-Chip
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We describe a high-speed FIFO circuit intended to compare the performance of an asynchronous FIFO with that of a clocked shift register using the same data path. The FIFO uses a pulse-like protocol to advance data along the pipeline. Use of this protocol requires careful management of circuit delays within its control circuits, as well as in the coordination of control signals with movement of bundled data. In simulations using hSpice, the throughput of the asynchronous circuit matches that of a two-phase clocked design. We fabricated 50 parts through MOSIS using their 0.6 micron design rules. We estimate from test measurements that the internal FIFO stages could support a maximum throughput from 930 million data items per second for the slowest of the 50 chips to 1126 million per second for the fastest chip. All 50 samples operated correctly as 3.3 V nominal Vdd varied from 1.67 V to over 4.8 V, with corresponding changes in operating speed and power as the supply voltage changed.