Communicating sequential processes
Communicating sequential processes
Communications of the ACM
Computer architecture: a quantitative approach
Computer architecture: a quantitative approach
The limitations to delay-insensitivity in asynchronous circuits
AUSCRYPT '90 Proceedings of the sixth MIT conference on Advanced research in VLSI
Programming in VLSI: from communicating processes to delay-insensitive circuits
Developments in concurrency and communication
Testing delay-insensitive circuits
Proceedings of the 1991 University of California/Santa Cruz conference on Advanced research in VLSI
Testing delay-insensitive circuits
Testing delay-insensitive circuits
Handshake circuits: an asynchronous architecture for VLSI programming
Handshake circuits: an asynchronous architecture for VLSI programming
Delay-insensitive multi-ring structures
Integration, the VLSI Journal - Special issue on asynchronous systems
Testing asynchronous circuits: a survey
Integration, the VLSI Journal
Phased logic: a design methodology for delay-insensitive, synchronous circuitry
Phased logic: a design methodology for delay-insensitive, synchronous circuitry
Four-phase micropipeline latch control circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Phased Logic: Supporting the Synchronous Design Paradigm with Delay-Insensitive Circuitry
IEEE Transactions on Computers
Telescopic units: increasing the average throughput of pipelined designs by adaptive latency control
DAC '97 Proceedings of the 34th annual Design Automation Conference
Skew-tolerant circuit design
Communicating sequential processes
Communications of the ACM
Modeling and forecasting of manufacturing variations (embedded tutorial)
Proceedings of the 2001 Asia and South Pacific Design Automation Conference
The tangram framework (embedded tutorial): asynchronous circuits for low power
Proceedings of the 2001 Asia and South Pacific Design Automation Conference
Chaff: engineering an efficient SAT solver
Proceedings of the 38th annual Design Automation Conference
Resynthesis and peephole transformations for the optimization of large-scale asynchronous systems
Proceedings of the 39th annual Design Automation Conference
The optimal logic depth per pipeline stage is 6 to 8 FO4 inverter delays
ISCA '02 Proceedings of the 29th annual international symposium on Computer architecture
Sequential Optimization of Asynchronous and Synchronous Finite-State Machines: Algorithms and Tools
Sequential Optimization of Asynchronous and Synchronous Finite-State Machines: Algorithms and Tools
Logic Synthesis and Verification
Design of Asynchronous Circuits Using Synchronous CAD Tools
IEEE Design & Test
Signal Graphs: From Self-Timed to Timed Ones
International Workshop on Timed Petri Nets
Slack Elasticity in Concurrent Computing
MPC '98 Proceedings of the Mathematics of Program Construction
Linear Test Times for Delay-Insensitive Circuits: a Compilation Strategy
Proceedings of the IFIP WG10.5 Working Conference on Asynchronous Design Methodologies
Proceedings of the tenth international symposium on Hardware/software codesign
Proceedings of the 40th annual Design Automation Conference
ASAP '96 Proceedings of the IEEE International Conference on Application-Specific Systems, Architectures, and Processors
Stretching quasi delay insensitivity by means of extended isochronic forks
ASYNC '95 Proceedings of the 2nd Working Conference on Asynchronous Design Methodologies
Single-Track Handshake Signaling with Application to Micropipelines and Handshake Circuits
ASYNC '96 Proceedings of the 2nd International Symposium on Advanced Research in Asynchronous Circuits and Systems
Control Resynthesis for Control-Dominated Asynchronous Designs
ASYNC '96 Proceedings of the 2nd International Symposium on Advanced Research in Asynchronous Circuits and Systems
A FIFO Ring Performance Experiment
ASYNC '97 Proceedings of the 3rd International Symposium on Advanced Research in Asynchronous Circuits and Systems
A Design Framework for Asynchronous/Synchronous Circuits Based on CHP to VHDL Translation
ASYNC '99 Proceedings of the 5th International Symposium on Advanced Research in Asynchronous Circuits and Systems
RAPPID: An Asynchronous Instruction Length Decoder
ASYNC '99 Proceedings of the 5th International Symposium on Advanced Research in Asynchronous Circuits and Systems
Asynchronous Design Using Commercial HDL Synthesis Tools
ASYNC '00 Proceedings of the 6th International Symposium on Advanced Research in Asynchronous Circuits and Systems
AMULET3i - An Asynchronous System-on-Chip
ASYNC '00 Proceedings of the 6th International Symposium on Advanced Research in Asynchronous Circuits and Systems
Synchronous Handshake Circuits
ASYNC '01 Proceedings of the 7th International Symposium on Asynchronous Circuits and Systems
Designing an Asynchronous Bus Interface
ASYNC '01 Proceedings of the 7th International Symposium on Asynchronous Circuits and Systems
FLEETzero: An Asynchronous Switching Experiment
ASYNC '01 Proceedings of the 7th International Symposium on Asynchronous Circuits and Systems
ASYNC '01 Proceedings of the 7th International Symposium on Asynchronous Circuits and Systems
SPA " A Synthesisable Amulet Core for Smartcard pplications
ASYNC '02 Proceedings of the 8th International Symposium on Asynchronus Circuits and Systems
High-Speed QDI Asynchronous Pipelines
ASYNC '02 Proceedings of the 8th International Symposium on Asynchronus Circuits and Systems
Checking Delay-Insensitivity: 104 Gates and Beyond
ASYNC '02 Proceedings of the 8th International Symposium on Asynchronus Circuits and Systems
Testing of Asynchronous Designs by "Inappropriate" Means: Synchronous Approach
ASYNC '02 Proceedings of the 8th International Symposium on Asynchronus Circuits and Systems
ASYNC '02 Proceedings of the 8th International Symposium on Asynchronus Circuits and Systems
The Lutonium: A Sub-Nanojoule Asynchronous 8051 Microcontroller
ASYNC '03 Proceedings of the 9th International Symposium on Asynchronous Circuits and Systems
SNAP: A Sensor-Network Asynchronous Processor
ASYNC '03 Proceedings of the 9th International Symposium on Asynchronous Circuits and Systems
A Coarse-Grain Phased Logic CPU
ASYNC '03 Proceedings of the 9th International Symposium on Asynchronous Circuits and Systems
The Design of an Asynchronous MIPS R3000 Microprocessor
ARVLSI '97 Proceedings of the 17th Conference on Advanced Research in VLSI (ARVLSI '97)
Logical timing (global synchronization of asynchronous arrays)
PAS '95 Proceedings of the First Aizu International Symposium on Parallel Algorithms/Architecture Synthesis
A doubly-latched asynchronous pipeline
ICCD '97 Proceedings of the 1997 International Conference on Computer Design (ICCD '97)
Synchronous Full-Scan for Asynchronous Handshake Circuits
Journal of Electronic Testing: Theory and Applications
Pipelined Asynchronous Circuits
Pipelined Asynchronous Circuits
Single-Track Asynchronous Pipeline Templates Using 1-of-N Encoding
Proceedings of the conference on Design, automation and test in Europe
Scan testing of micropipelines
VTS '95 Proceedings of the 13th IEEE VLSI Test Symposium
Optimum Power/Performance Pipeline Depth
Proceedings of the 36th annual IEEE/ACM International Symposium on Microarchitecture
Bridging the Gap between Asynchronous Design and Designers
VLSID '04 Proceedings of the 17th International Conference on VLSI Design
A Logic Level Design Methodology for a Secure DPA Resistant ASIC or FPGA Implementation
Proceedings of the conference on Design, automation and test in Europe - Volume 1
From Synchronous to Asynchronous: An Automatic Approach
Proceedings of the conference on Design, automation and test in Europe - Volume 2
Statistical Timing Analysis Using Bounds
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Logically Determined Design: Clockless System Design with NULL Convention Logic
Logically Determined Design: Clockless System Design with NULL Convention Logic
Design and Analysis of Dual-Rail Circuits for Security Applications
IEEE Transactions on Computers
Delay Insensitive Encoding and Power Analysis: A Balancing Act
ASYNC '05 Proceedings of the 11th IEEE International Symposium on Asynchronous Circuits and Systems
A Multiplexor Based Test Method for Self-Timed Circuits
ASYNC '05 Proceedings of the 11th IEEE International Symposium on Asynchronous Circuits and Systems
The Challenges of Hardware Synthesis from C-Like Languages
Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
A 3.84 gbits/s AES crypto coprocessor with modes of operation in a 0.18-μm CMOS technology
GLSVLSI '05 Proceedings of the 15th ACM Great Lakes symposium on VLSI
An Automated Fine-Grain Pipelining Using Domino Style Asynchronous Library
ACSD '05 Proceedings of the Fifth International Conference on Application of Concurrency to System Design
An ultra-low energy asynchronous processor for Wireless Sensor Networks
ASYNC '06 Proceedings of the 12th IEEE International Symposium on Asynchronous Circuits and Systems
Optimal Technology Mapping and Cell Merger for Asynchronous Threshold Networks
ASYNC '06 Proceedings of the 12th IEEE International Symposium on Asynchronous Circuits and Systems
Slack Matching Asynchronous Designs
ASYNC '06 Proceedings of the 12th IEEE International Symposium on Asynchronous Circuits and Systems
Slack Matching Quasi Delay-Insensitive Circuits
ASYNC '06 Proceedings of the 12th IEEE International Symposium on Asynchronous Circuits and Systems
Power Attacks on Secure Hardware Based on Early Propagation of Data
IOLTS '06 Proceedings of the 12th IEEE International Symposium on On-Line Testing
Cost-aware synthesis of asynchronous circuits based on partial acknowledgement
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
Leveraging protocol knowledge in slack matching
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
Principles of Asynchronous Circuit Design: A Systems Perspective
Principles of Asynchronous Circuit Design: A Systems Perspective
Automated design of cryptographic devices resistant to multiple side-channel attacks
CHES'06 Proceedings of the 8th international conference on Cryptographic Hardware and Embedded Systems
Security evaluation against electromagnetic analysis at design time
CHES'05 Proceedings of the 7th international conference on Cryptographic hardware and embedded systems
Prototype IC with WDDL and differential routing – DPA resistance assessment
CHES'05 Proceedings of the 7th international conference on Cryptographic hardware and embedded systems
Implementation of handshake components
CSP'04 Proceedings of the 2004 international conference on Communicating Sequential Processes: the First 25 Years
Hardware compilation of application-specific memory-access interconnect
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Desynchronization: Synthesis of Asynchronous Circuits From Synchronous Specifications
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Automated Synchronous-to-Asynchronous Circuits Conversion: A Survey
Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
SpiNNaker: Design and Implementation of a GALS Multicore System-on-Chip
ACM Journal on Emerging Technologies in Computing Systems (JETC)
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The number of gates on a chip is quickly growing toward and beyond the one billion mark. Keeping all the gates running at the beat of a single or a few rationally related clocks is becoming impossible. In static timing analysis process variations and signal integrity issues stretch the timing margins to the point where they become too conservative and result in significant overdesign. Importance and difficulty of such problems push some developers to once again turn to asynchronous alternatives. However, the electronics industry for the most part is still reluctant to adopt asynchronous design (with a few notable exceptions) due to a common belief that we still lack a commercial-quality Electronic Design Automation tools (similar to the synchronous RTL-to-GDSII flow) for asynchronous circuits. The purpose of this paper is to counteract this view by presenting design flows that can tackle large designs without significant changes with respect to synchronous design flow. We are limiting ourselves to four design flows that we believe to be closest to this goal. We start from the Tangram flow, because it is the most commercially proven and it is one of the oldest from a methodological point of view. The other three flows (Null Convention Logic, de-synchronization, and gate-level pipelining) could be considered together as asynchronous re-implementations of synchronous (RTL-or gate-level) specifications. The main common idea is substituting the global clocks by local synchronizations. Their most important aspect is to open the possibility to implement large legacy synchronous designs in an almost "push button" manner, where all asynchronous machinery is hidden, so that synchronous RTL designers do not need to be re-educated. These three flows offer a trade-off from very low overhead, almost synchronous implementations, to very high performance, extremely robust dual-rail pipelines.