Fast statistical timing analysis by probabilistic event propagation
Proceedings of the 38th annual Design Automation Conference
A general probabilistic framework for worst case timing analysis
Proceedings of the 39th annual Design Automation Conference
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Statistical Timing Analysis of Combinational Circuits
ICCD '92 Proceedings of the 1991 IEEE International Conference on Computer Design on VLSI in Computer & Processors
DAC '83 Proceedings of the 20th Design Automation Conference
Timing Verification and the Timing Analysis program
DAC '82 Proceedings of the 19th Design Automation Conference
A New Statistical Approach to Timing Analysis of VLSI Circuits
VLSID '98 Proceedings of the Eleventh International Conference on VLSI Design: VLSI for Signal Processing
Computation and Refinement of Statistical Bounds on Circuit Delay
Proceedings of the 40th annual Design Automation Conference
A statistical model for estimating the effect of process variations on crosstalk noise
Proceedings of the 2004 international workshop on System level interconnect prediction
Pattern Selection for Testing of Deep Sub-Micron Timing Defects
Proceedings of the conference on Design, automation and test in Europe - Volume 2
STAC: statistical timing analysis with correlation
Proceedings of the 41st annual Design Automation Conference
Novel sizing algorithm for yield improvement under process variation in nanometer technology
Proceedings of the 41st annual Design Automation Conference
Placement Method Targeting Predictability Robustness and Performance
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Toward stochastic design for digital circuits: statistical static timing analysis
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
Correlation-aware statistical timing analysis with non-gaussian delay distributions
Proceedings of the 42nd annual Design Automation Conference
Static statistical timing analysis for latch-based pipeline designs
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Statistical crosstalk aggressor alignment aware interconnect delay calculation
Proceedings of the 2006 international workshop on System-level interconnect prediction
Statistical Bellman-Ford algorithm with an application to retiming
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
Implementation of MOSFET based capacitors for digital applications
GLSVLSI '06 Proceedings of the 16th ACM Great Lakes symposium on VLSI
Statistical gate delay calculation with crosstalk alignment consideration
GLSVLSI '06 Proceedings of the 16th ACM Great Lakes symposium on VLSI
Impact of Body Bias on Delay Fault Testing of Sub-100 nm CMOS Circuits
Journal of Electronic Testing: Theory and Applications
Guaranteeing performance yield in high-level synthesis
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
Design automation of real-life asynchronous devices and systems
Foundations and Trends in Electronic Design Automation
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
Proceedings of the conference on Design, automation and test in Europe
Signal probability based statistical timing analysis
Proceedings of the conference on Design, automation and test in Europe
Accelerating statistical static timing analysis using graphics processing units
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
Timing modeling for digital sub-threshold circuits
Proceedings of the Conference on Design, Automation and Test in Europe
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The growing impact of within-die process variation has created the need for statistical timing analysis, where gate delays are modeled as random variables. Statistical timing analysis has traditionally suffered from exponential run time complexity with circuit size, due to the dependencies created by reconverging paths in the circuit. In this paper we propose a new approach to statistical timing analysis which uses statistical bounds. First, we provide a formal definition of the statistical delay of a circuit and derive a statistical timing analysis method from this definition. Since this method for finding the exact statistical delay has exponential run time complexity with circuit size, we also propose a new method for computing statistical bounds which has linear run time complexity. We prove the correctness of the proposed bounds. Since we provide both a lower and upper bound on the true statistical delay we can determine the quality of the bounds. The proposed methods were implemented and tested on benchmark circuits. The results demonstrate that the proposed bounds have only a small error.