Statistical gate delay model considering multiple input switching
Proceedings of the 41st annual Design Automation Conference
Statistical Timing Analysis for Intra-Die Process Variations with Spatial Correlations
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Statistical Timing Analysis Using Bounds
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Modeling Within-Die Spatial Correlation Effects for Process-Design Co-Optimization
ISQED '05 Proceedings of the 6th International Symposium on Quality of Electronic Design
Statistical crosstalk aggressor alignment aware interconnect delay calculation
Proceedings of the 2006 international workshop on System-level interconnect prediction
Robust extraction of spatial correlation
Proceedings of the 2006 international symposium on Physical design
Statistical gate delay calculation with crosstalk alignment consideration
GLSVLSI '06 Proceedings of the 16th ACM Great Lakes symposium on VLSI
Lens aberration aware timing-driven placement
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Refined statistical static timing analysis through
Proceedings of the 43rd annual Design Automation Conference
An IC manufacturing yield model considering intra-die variations
Proceedings of the 43rd annual Design Automation Conference
Proceedings of the 43rd annual Design Automation Conference
A general framework for spatial correlation modeling in VLSI design
Proceedings of the 44th annual Design Automation Conference
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Noninvasive leakage power tomography of integrated circuits by compressive sensing
Proceedings of the 13th international symposium on Low power electronics and design
Proceedings of the 46th Annual Design Automation Conference
Dominant critical gate identification for power and yield optimization in logic circuits
Proceedings of the 20th symposium on Great lakes symposium on VLSI
Hybrid modeling of non-stationary process variations
Proceedings of the 48th Design Automation Conference
Exploring sub-20nm FinFET design with predictive technology models
Proceedings of the 49th Annual Design Automation Conference
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Statistical timing analysis needs a priori knowledge of process variations. Lack of such a priori knowledge of process variations prevents accurate statistical timing analysis, for which foundry confidentiality policy has largely been blamed. A significant part of process variations are design specific, and can only be extracted from production chip performance statistics. In this paper, I adopt the homogeneous isotropic random field model for intra-die random variations, apply fast Fourier transform (FFT) to simulate a homogeneous isotropic random field, obtain corners for Monte Carlo SPICE simulation of timing critical paths in a VLSI circuit, and apply regression to match production chip performance statistics. Experimental results based on a timing critical path in an industry design with 65nm Predictive Technology Models reveal constant mean, increased standard deviation, and decreased skewness of a signal propagation path delay as spatial correlation increases. The proposed spatial correlation extraction technique can be applied in a chip tapeout process, where process variations extracted from an early tapeout help to improve statistical timing analysis accuracy and guide engineering change order of subsequent tapeouts.