Parameter variations and impact on circuits and microarchitecture
Proceedings of the 40th annual Design Automation Conference
Proceedings of the 2003 international symposium on Low power electronics and design
Full-chip analysis of leakage power under process variations, including spatial correlations
Proceedings of the 42nd annual Design Automation Conference
Variability inspired implementation selection problem
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Fast and effective gate-sizing with multiple-Vt assignment using generalized Lagrangian Relaxation
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Discrete Vt assignment and gate sizing using a self-snapping continuous formulation
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Digital Circuit Optimization via Geometric Programming
Operations Research
Statistical Gate Sizing for Yield Enhancement at Post Layout Level
ISVLSI '07 Proceedings of the IEEE Computer Society Annual Symposium on VLSI
A novel criticality computation method in statistical timing analysis
Proceedings of the conference on Design, automation and test in Europe
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
Proceedings of the conference on Design, automation and test in Europe
Incremental criticality and yield gradients
Proceedings of the conference on Design, automation and test in Europe
Fast and accurate statistical criticality computation under process variations
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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With increasing process variations, low-VT swapping is an effective technique that can be used to improve timing yield without having to modify a design following placement and routing. Gate criticality, defined as the probability that a gate lies on a critical path, forms the basis for existing low-VT swapping techniques. This paper presents a simulation-based study that challenges the effectiveness of low-VT swapping based on the conventional definition of gate criticality, especially as random process variations increase with technology scaling. We introduce dominant gate criticality to address the drawbacks of the conventional definition of gate criticality, and formulate dominant critical gate ranking in the presence of process variations as an optimization problem. Simulation results for 12 benchmark circuits from the ISCAS and OpenSPARC suites to achieve timing yields of 95% and 98% indicate that low-VT swapping based on dominant gate criticality reduces leakage power overhead by 61% and 42% for independent and correlated process variations, respectively, over low-VT swapping based on conventional gate criticality.