Fast and effective gate-sizing with multiple-Vt assignment using generalized Lagrangian Relaxation

Authors:
Hsinwei Chou;Yu-Hao Wang;Charlie Chung-Ping Chen
Affiliations:
University of Wisconsin, Madison;Incentia Design Systems, Inc.;National Taiwan University
Venue:
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Year:
2005

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Abstract

Simultaneous gate-sizing with multiple Vt assignment for delay and power optimization is a complicated task in modern custom designs. In this work, we make the key contribution of a novel gate-sizing and multi-Vt assignment technique based on generalized Lagrangian Relaxation. Experimental results show that our technique exhibits linear runtime and memory usage, and can effectively tune circuits with over 15,000 variables and 8,000 constraints in under 8 minutes (250x faster than state-of-the-art optimization solvers).