Algorithms for library-specific sizing of combinational logic
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
RICE: Rapid interconnect circuit evaluator
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
Gate sizing for constrained delay/power/area optimization
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special issue on low power electronics and design
Fast and exact simultaneous gate and wire sizing by Lagrangian relaxation
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
Design and optimization of dual-threshold circuits for low-voltage low-power applications
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Stand-by power minimization through simultaneous threshold voltage selection and circuit sizing
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Low power synthesis of dual threshold voltage CMOS VLSI circuits
ISLPED '99 Proceedings of the 1999 international symposium on Low power electronics and design
Standby power optimization via transistor sizing and dual threshold voltage assignment
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Proceedings of the 2003 international symposium on Low power electronics and design
Fast and effective gate-sizing with multiple-Vt assignment using generalized Lagrangian Relaxation
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Discrete Vt assignment and gate sizing using a self-snapping continuous formulation
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Gate sizing for cell library-based designs
Proceedings of the 44th annual Design Automation Conference
Proceedings of the 13th international symposium on Low power electronics and design
Simultaneous Vtselection and assignment for leakage optimization
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
GPU-based parallelization for fast circuit optimization
Proceedings of the 46th Annual Design Automation Conference
Eyecharts: constructive benchmarking of gate sizing heuristics
Proceedings of the 47th Design Automation Conference
Lagrangian relaxation for gate implementation selection
Proceedings of the 2011 international symposium on Physical design
GPU-Based Parallelization for Fast Circuit Optimization
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Shedding physical synthesis area bloat
VLSI Design - Special issue on CAD for Gigascale SoC Design and Verification Solutions
Exploiting dynamic micro-architecture usage in gate sizing
Microprocessors & Microsystems
Gate sizing and device technology selection algorithms for high-performance industrial designs
Proceedings of the International Conference on Computer-Aided Design
Fast thermal analysis on GPU for 3D-ICs with integrated microchannel cooling
Proceedings of the International Conference on Computer-Aided Design
Discrete sizing for leakage power optimization in physical design: A comparative study
ACM Transactions on Design Automation of Electronic Systems (TODAES) - Special section on adaptive power management for energy and temperature-aware computing systems
An efficient algorithm for library-based cell-type selection in high-performance low-power designs
Proceedings of the International Conference on Computer-Aided Design
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Gate sizing and threshold voltage (Vt) assignment are popular techniques for circuit timing and power optimization. Existing methods, by and large, are either sensitivity-driven heuristics or based on rounding continuous optimization solutions. Sensitivity-drive heuristics are easily trapped in local optimum and the rounding is subject to remarkable errors. In this paper, we propose a systematic combinatorial approach for simultaneous gate sizing and Vt assignment. The core ideas of this approach include consistency relaxation and coupled bi-directional search. Our algorithm is compared with a state-of-the-art previous work on benchmark circuits. The results from our algorithm can lead to about 24% less power dissipation subject to the same timing constraints.