A performance optimization method by gate sizing using statistical static timing analysis
ISPD '00 Proceedings of the 2000 international symposium on Physical design
Fast post-placement rewiring using easily detectable functional symmetries
Proceedings of the 37th Annual Design Automation Conference
In-place delay constrained power optimization using functional symmetries
Proceedings of the conference on Design, automation and test in Europe
Layout-driven hot-carrier degradation minimization using logic restructuring techniques
Proceedings of the 38th annual Design Automation Conference
Functional correlation analysis in crosstalk induced critical paths identification
Proceedings of the 38th annual Design Automation Conference
Logical and physical design: a flow perspective
Logic Synthesis and Verification
Logic Synthesis and Verification
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Dual Supply Voltage Scaling in a Conventional Power-Driven Logic Synthesis Environment
PATMOS '02 Proceedings of the 12th International Workshop on Integrated Circuit Design. Power and Timing Modeling, Optimization and Simulation
Clock and Power Gating with Timing Closure
IEEE Design & Test
Quality of EDA CAD Tools: Definitions, Metrics and Directions
ISQED '00 Proceedings of the 1st International Symposium on Quality of Electronic Design
Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Improving run times by pruned application of synthesis transforms
SBCCI '05 Proceedings of the 18th annual symposium on Integrated circuits and system design
LOTUS: Leakage Optimization under Timing Uncertainty for Standard-cell designs
ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
Proceedings of the 43rd annual Design Automation Conference
Pattern sensitive placement for manufacturability
Proceedings of the 2007 international symposium on Physical design
Gate sizing for cell library-based designs
Proceedings of the 44th annual Design Automation Conference
Discrete buffer and wire sizing for link-based non-tree clock networks
Proceedings of the 2008 international symposium on Physical design
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
PaRS: fast and near-optimal grid-based cell sizing for library-based design
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
A new algorithm for simultaneous gate sizing and threshold voltage assignment
Proceedings of the 2009 international symposium on Physical design
A fuzzy optimization approach for variation aware power minimization during gate sizing
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
GPU-based parallelization for fast circuit optimization
Proceedings of the 46th Annual Design Automation Conference
Gate sizing for cell-library-based designs
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Gate sizing by Lagrangian relaxation revisited
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
PaRS: parallel and near-optimal grid-based cell sizing for library-based design
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Physical realization oriented area-power-delay tradeoff exploration
SOC'09 Proceedings of the 11th international conference on System-on-chip
A new algorithm for simultaneous gate sizing and threshold voltage assignment
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Parameterized MAC unit generation for a scalable embedded DSP core
Microprocessors & Microsystems
Post-manufacture tuning for nano-CMOS yield recovery using reconfigurable logic
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Eyecharts: constructive benchmarking of gate sizing heuristics
Proceedings of the 47th Design Automation Conference
A data capturing method for buses on chip
IEEE Transactions on Circuits and Systems Part I: Regular Papers
Discrete buffer and wire sizing for link-based non-tree clock networks
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Pattern sensitive placement perturbation for manufacturability
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
GPU-Based Parallelization for Fast Circuit Optimization
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Approximation scheme for restricted discrete gate sizing targeting delay minimization
Journal of Combinatorial Optimization
A theoretical probabilistic simulation framework for dynamic power estimation
Proceedings of the International Conference on Computer-Aided Design
Gate sizing and device technology selection algorithms for high-performance industrial designs
Proceedings of the International Conference on Computer-Aided Design
Discrete sizing for leakage power optimization in physical design: A comparative study
ACM Transactions on Design Automation of Electronic Systems (TODAES) - Special section on adaptive power management for energy and temperature-aware computing systems
An efficient algorithm for library-based cell-type selection in high-performance low-power designs
Proceedings of the International Conference on Computer-Aided Design
Sensitivity-guided metaheuristics for accurate discrete gate sizing
Proceedings of the International Conference on Computer-Aided Design
Proceedings of the Conference on Design, Automation and Test in Europe
Fast and efficient lagrangian relaxation-based discrete gate sizing
Proceedings of the Conference on Design, Automation and Test in Europe
VLSI Design - Special issue on New Algorithmic Techniques for Complex EDA Problems
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Gate sizing has a significant impact on the delay, power dissipation, and area of the final circuit. It consists of choosing for each node of a mapped circuit a gate implementation in the library so that a cost function is optimized under some constraints. For instance, one wants to minimize the power consumption and/or the area of a circuit under some user-defined delay constraints, or to obtain the fastest circuit within a given power budget. Although this technology-dependent optimization has been investigated for years, the proposed approaches sometimes rely on assumptions, cost models, or algorithms that make them unrealistic or impossible to apply on real-life large circuits. We discussed here a gate sizing algorithm (GS), and show how it is used to achieve constrained optimization. It can be applied on large circuits within a reasonable CPU time, e.g., minimizing the power of a 10000 gates circuit under some delay constraint in 2 h.