An exact algorithm for low power library-specific gate re-sizing
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Gate sizing for constrained delay/power/area optimization
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special issue on low power electronics and design
Gate sizing using a statistical delay model
DATE '00 Proceedings of the conference on Design, automation and test in Europe
A New Statistical Approach to Timing Analysis of VLSI Circuits
VLSID '98 Proceedings of the Eleventh International Conference on VLSI Design: VLSI for Signal Processing
A probabilistic approach to clock cycle prediction
Proceedings of the 8th ACM/IEEE international workshop on Timing issues in the specification and synthesis of digital systems
A Statistical Gate-Delay Model Considering Intra-Gate Variability
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
A New Method for Design of Robust Digital Circuits
ISQED '05 Proceedings of the 6th International Symposium on Quality of Electronic Design
A statistical gate delay model for intra-chip and inter-chip variabilities
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
A novel approach for variation aware power minimization during gate sizing
Proceedings of the 2006 international symposium on Low power electronics and design
A fuzzy optimization approach for variation aware power minimization during gate sizing
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Variation-aware multimetric optimization during gate sizing
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Dynamic clock stretching for variation compensation in VLSI circuit design
ACM Journal on Emerging Technologies in Computing Systems (JETC)
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