LATTIS: an iterative speedup heuristic for mapped logic
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
An exact algorithm for low power library-specific gate re-sizing
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Gate sizing for constrained delay/power/area optimization
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special issue on low power electronics and design
Fast and exact simultaneous gate and wire sizing by Lagrangian relaxation
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
A performance optimization method by gate sizing using statistical static timing analysis
ISPD '00 Proceedings of the 2000 international symposium on Physical design
Gate sizing using a statistical delay model
DATE '00 Proceedings of the conference on Design, automation and test in Europe
Reducing the frequency gap between ASIC and custom designs: a custom perspective
Proceedings of the 38th annual Design Automation Conference
Fast statistical timing analysis by probabilistic event propagation
Proceedings of the 38th annual Design Automation Conference
Uncertainty-aware circuit optimization
Proceedings of the 39th annual Design Automation Conference
Technology-based transformations
Logic Synthesis and Verification
Lancelot: A FORTRAN Package for Large-Scale Nonlinear Optimization (Release A)
Lancelot: A FORTRAN Package for Large-Scale Nonlinear Optimization (Release A)
Statistical Timing Analysis of Combinational Circuits
ICCD '92 Proceedings of the 1991 IEEE International Conference on Computer Design on VLSI in Computer & Processors
Gate sizing using Lagrangian relaxation combined with a fast gradient-based pre-processing step
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Statistical Timing Analysis Considering Spatial Correlations using a Single Pert-Like Traversal
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
A sequential quadratic programming approach to concurrent gate and wire sizing
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Statistical timing analysis using bounds and selective enumeration
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Yield-area optimizations of digital circuits using non-dominated sorting genetic algorithm (YOGA)
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
Extraction of statistical timing profiles using test data
Proceedings of the 44th annual Design Automation Conference
A fuzzy optimization approach for variation aware power minimization during gate sizing
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Variation-aware multimetric optimization during gate sizing
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Delay uncertainty reduction by gate splitting
IEEE Transactions on Circuits and Systems II: Express Briefs
Post-manufacture tuning for nano-CMOS yield recovery using reconfigurable logic
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A data capturing method for buses on chip
IEEE Transactions on Circuits and Systems Part I: Regular Papers
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A new approach for enhancing the process-variation tolerance of digital circuits is described. We extend recent advances in statistical timing analysis into an optimization framework. Our objective is to reduce the performance variance of a technology-mapped circuit where delays across elements are represented by random variables which capture the manufacturing variations. We introduce the notion of statistical critical paths, which account for both means and variances of performance variation. An optimization engine is used to size gates with a goal of reducing the timing variance along the statistical critical paths. We apply a pair of nested statistical analysis methods deploying a slower more accurate approach for tracking statistical critical paths and a fast engine for evaluation of gate size assignments. We derive a new approximation for the max operation on random variables which is deployed for the faster inner engine. Circuit optimization is carried out using a gain-based algorithm that terminates when constraints are satisfied or no further improvements can be made. We show optimization results that demonstrate an average of 72% reduction in performance variation at the expense of average 20% increase in design area.