Gate sizing using a statistical delay model

A performance optimization method by gate sizing using statistical static timing analysis

ISPD '00 Proceedings of the 2000 international symposium on Physical design

A statistical static timing analysis considering correlations between delays

Proceedings of the 2001 Asia and South Pacific Design Automation Conference

Static timing analysis

Logic Synthesis and Verification

A probabilistic approach to clock cycle prediction

Proceedings of the 8th ACM/IEEE international workshop on Timing issues in the specification and synthesis of digital systems

Novel sizing algorithm for yield improvement under process variation in nanometer technology

Proceedings of the 41st annual Design Automation Conference

Placement Method Targeting Predictability Robustness and Performance

Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design

Statistical Timing Analysis for Intra-Die Process Variations with Spatial Correlations

Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design

Toward stochastic design for digital circuits: statistical static timing analysis

Proceedings of the 2004 Asia and South Pacific Design Automation Conference

Improving the Process-Variation Tolerance of Digital Circuits Using Gate Sizing and Statistical Techniques

Proceedings of the conference on Design, Automation and Test in Europe - Volume 1

Statistical Timing Based Optimization using Gate Sizing

Proceedings of the conference on Design, Automation and Test in Europe - Volume 1

Statistical Modeling of Pipeline Delay and Design of Pipeline under Process Variation to Enhance Yield in sub-100nm Technologies

Proceedings of the conference on Design, Automation and Test in Europe - Volume 2

A New Method for Design of Robust Digital Circuits

ISQED '05 Proceedings of the 6th International Symposium on Quality of Electronic Design

An efficient algorithm for statistical minimization of total power under timing yield constraints

Proceedings of the 42nd annual Design Automation Conference

Robust gate sizing by geometric programming

Proceedings of the 42nd annual Design Automation Conference

Circuit optimization using statistical static timing analysis

Proceedings of the 42nd annual Design Automation Conference

Delay variation tolerance for domino circuits

ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference

Application of fast SOCP based statistical sizing in the microprocessor design flow

GLSVLSI '06 Proceedings of the 16th ACM Great Lakes symposium on VLSI

Statistical technology mapping for parametric yield

ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design

Gate sizing using incremental parameterized statistical timing analysis

ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design

Statistical gate sizing for timing yield optimization

ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design

Impact of Body Bias on Delay Fault Testing of Sub-100 nm CMOS Circuits

Journal of Electronic Testing: Theory and Applications

Soft-edge flip-flops for improved timing yield: design and optimization

Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design

Simultaneous optimization of total power, crosstalk noise, and delay under uncertainty

Proceedings of the 18th ACM Great Lakes symposium on VLSI

An expected-utility based approach to variation aware VLSI optimization under scarce information

Proceedings of the 13th international symposium on Low power electronics and design

Robust interconnect communication capacity algorithm by geometric programming

Proceedings of the 2009 international symposium on Physical design

Statistical static timing analysis: A survey

Integration, the VLSI Journal

Statistical analysis of circuit timing using majorization

Communications of the ACM - A Blind Person's Interaction with Technology

Variation-aware multimetric optimization during gate sizing

ACM Transactions on Design Automation of Electronic Systems (TODAES)

Variable input delay CMOS logic for low power design

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Design of variable input delay gates for low dynamic power circuits

PATMOS'05 Proceedings of the 15th international conference on Integrated Circuit and System Design: power and Timing Modeling, Optimization and Simulation