Applied multivariate statistical analysis
Applied multivariate statistical analysis
Gate sizing using a statistical delay model
DATE '00 Proceedings of the conference on Design, automation and test in Europe
Noise Analysis under Capacitive and Inductive Coupling for High Speed Circuits
DELTA '02 Proceedings of the The First IEEE International Workshop on Electronic Design, Test and Applications (DELTA '02)
Crosstalk Noise Estimation for Generic RC Trees
ICCD '01 Proceedings of the International Conference on Computer Design: VLSI in Computers & Processors
Convex Optimization
A methodology to improve timing yield in the presence of process variations
Proceedings of the 41st annual Design Automation Conference
Novel sizing algorithm for yield improvement under process variation in nanometer technology
Proceedings of the 41st annual Design Automation Conference
Closed-form expressions of distributed RLC interconnects for analysis of on-chip inductance effects
Proceedings of the 41st annual Design Automation Conference
Robust gate sizing by geometric programming
Proceedings of the 42nd annual Design Automation Conference
OPERA: optimization with ellipsoidal uncertainty for robust analog IC design
Proceedings of the 42nd annual Design Automation Conference
Information Theoretic Capacity of Long On-chip Interconnects in the Presence of Crosstalk
ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
Information theoretic approach to address delay and reliability in long on-chip interconnects
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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This paper proposes a new model for interconnect communication capacity in the presence of process variations. Different from previous research works, this model, for the first time, reveals the dependency of interconnect communication capacity on its parasitic parameters. A new method based on Uncertainty Ellipsoid Method (UEM) is applied to optimize the interconnect capacity considering random parameters variations. This new approach incorporates both spatial correlations of intra-die width and parameters variations in the optimization procedure. As is well known, process variation introduces perturbations in the transfer function of interconnect networks. The perturbed transfer function in turn causes variations in the Bit Error Rate (BER). Becoming random, the perturbed BER leads to a changing communication capacity. Based on robust communication theory, we propose a new capacity model which is a function of interconnect geometric parameters. With the help of Geometric Programming (GP) procedure, we use the new model to conduct optimization with regard to the design parameters. Experimental results show that the new model provides less than 7:3% mean square error in capacity prediction comparing with Monte-Carlo method. Based on this bit error value, GP technique is applied to determine the optimal solution, which in return guides the fabrication of interconnects.