Optimization of inductor circuits via geometric programming
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Design for Variability in DSM Technologies
ISQED '00 Proceedings of the 1st International Symposium on Quality of Electronic Design
Convex Optimization
Impact of Design-Manufacturing Interface on SoC Design Methodologies
IEEE Design & Test
Efficient handling of operating range and manufacturing line variations in analog cell synthesis
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Optimal design of a CMOS op-amp via geometric programming
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Worst-case analysis and optimization of VLSI circuit performances
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Chameleon ART: a non-optimization based analog design migration framework
Proceedings of the 43rd annual Design Automation Conference
Robust system level design with analog platforms
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
Parameterized macromodeling for analog system-level design exploration
Proceedings of the 44th annual Design Automation Conference
Statistical performance modeling and optimization
Foundations and Trends in Electronic Design Automation
Classification of analog synthesis tools based on their architecture selection mechanisms
Integration, the VLSI Journal
Evaluation of voltage interpolation to address process variations
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
Robust interconnect communication capacity algorithm by geometric programming
Proceedings of the 2009 international symposium on Physical design
Yield-driven iterative robust circuit optimization algorithm
Proceedings of the 46th Annual Design Automation Conference
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Exploiting reconfigurability for low-cost in-situ test and monitoring of digital PLLs
Proceedings of the 47th Design Automation Conference
A platform-based methodology for system-level mixed-signal design
EURASIP Journal on Embedded Systems - Special issue on design methodologies and innovative architectures for mixed-signal embedded systems
Automating design of voltage interpolation to address process variations
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
CalCS: SMT solving for non-linear convex constraints
Proceedings of the 2010 Conference on Formal Methods in Computer-Aided Design
An algorithm for exploiting modeling error statistics to enable robust analog optimization
Proceedings of the International Conference on Computer-Aided Design
Operating-point driven formulation for analog computer-aided design
Analog Integrated Circuits and Signal Processing
Modeling and design of CMOS analog circuits through hierarchical abstraction
Integration, the VLSI Journal
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As the design-manufacturing interface becomes increasingly complicated with IC technology scaling, the corresponding process variability poses great challenges for nanoscale analog/RF design. Design optimization based on the enumeration of process corners has been widely used , but can suffer from inefficiency and overdesign. In this paper we propose to formulate the analog and RF design with variability problem as a special type of robust optimization problem, namely robust geometric programming. The statistical variations in both the process parameters and design variables are captured by a pre-specified confidence ellipsoid. Using such optimization with ellipsoidal uncertainy approach, robust design can be obtained with guaranteed yield bound and lower design cost, and most importantly, the problem size grows linearly with number of uncertain parameters. Numerical examples demonstrate the efficiency and reveal the trade-off between the design cost versus the yield requirement. We will also demonstrate significant improvement in the design cost using this approach compared with corner-enumeration optimization.