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Proceedings of the 42nd annual Design Automation Conference
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Proceedings of the 42nd annual Design Automation Conference
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IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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Analog Integrated Circuits and Signal Processing
Formal verification of analog circuit parameters across variation utilizing SAT
Proceedings of the Conference on Design, Automation and Test in Europe
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Analog Integrated Circuits and Signal Processing
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Analog Integrated Circuits and Signal Processing
Proceedings of the International Conference on Computer-Aided Design
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This paper presents an overview of methods to automatically generate posynomial response surface models for the performance characteristics of analog integrated circuits based on numerical simulation data. The methods are capable of generating posynomial performance expressions for both linear and nonlinear circuits and circuit characteristics, at SPICE-level accuracy. This approach allows for automatic generation of an accurate sizing model for a circuit that composes a geometric program that fully describes the analog circuit sizing problem. The automatic generation avoids the time-consuming and approximate nature of handcrafted analytic model generation. The methods are based on techniques from design of experiments and response surface modeling. Attention is paid to estimating the relative "goodness-of-fit" of the generated models. Experimental results illustrate the capabilities and effectiveness of the presented methods.